Avaya 03-300430 User Manual

This test is destructive.
The End Loopback/Span test terminates an active loopback or span test on a UDS1 circuit 
pack. Bit error counting against the received test pattern stream is terminated and sending of 
the framed 3-in-24 test pattern is halted. If either the CPE Loop-Back Jack or the far-end CSU is 
looped, the appropriate loopback deactivate code is sent. If the loopback cannot be 
deactivated, then the test returns FAIL, and a MINOR alarm is noted in the alarm log until the 
loopback is cleared.
The test is highly destructive and can only be initiated by a test ds1-loop location 
end-loopback/span-test command. Since only one of these three different long-duration 

loopback/span tests can be active at a time, the UDS1-BD circuit pack knows which loopback/
span test to terminate.
Each trunk or port on the UDS1 Interface circuit pack must be busied out using busyout 
board location before running this End Loopback/Span test.

PASS

A single bit error has been successfully injected into an active framed 

3-in-24 test pattern.

0

NO

BOARD

The test could not relate the internal ID to the port (no board). This could 
be due to incorrect translations, no board is inserted, an incorrect board is 
inserted, or an insane board is inserted.

1. Verify that the board’s translations are correct. Execute add ds1 

location command to administer the UDS1 interface if it is not 

already administered.

2. If the board was already administered correctly, check the error log to 

determine whether the board is hyperactive. If so, the board was shut 
down. Reseating the board will re-initialize it.

3. If the board was found to be correctly inserted in step 1, enter 

busyout board location.

4. Enter reset board location.
5. Enter release board location.
6. Enter test board location long.

This should re-establish the linkage between the internal ID and the port.

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