Sun X4100 0915ALEB30-HD 0915ALEB30 User Manual
Product codes
0915ALEB30
Sun Microsystems, Inc.
Memory Interface
In traditional x86 Northbridge/Southbridge architectures, processors share a memory controller and are not directly connected to
one another. Memory transactions must propogate through the Northbridge chip fabric. This presents a bottleneck at the front-side
bus that greatly reduces productivity and performance potential. In a Direct Connect Architecture, each CPU has its own integrated
memory controller, which allows for more linear, symmetrical multiprocessing and optimized memory performance. This direct con-
nection to the memory controller significantly reduces the memory latency seen by the processor. Latency will continue to drop as
the processor frequency scales.
Additionally, hardware and software memory pre-fetching mechanisms can further reduce the effective memory latency seen by the
processor. This reduction in memory latency, coupled with the additional increase in memory bandwidth available directly to the
processor (resulting from this platform architecture design optimization), is critical as it greatly enhances system performance across
all application segments.
Chip-to-Chip Interconnect
Current interface schemes offer throughput performance on the order of 266 MB/sec. to 1 GB/sec. Although these rates may be suffi-
cient for desktop platforms, workstation, server, and other future platforms require a more robust interface. The simultaneous inte-
gration of high-speed technologies (such as Gigabit Ethernet, PCI-E, and the InfiniBand Architecture) onto high-end platforms will
quickly dwarf the bandwidth capabilities of existing interfaces. Direct Connect Architecture using HyperTransport Technology pro-
vides a high-speed, chip- to-chip interconnect that virtually eliminates the I/O performance bottleneck while providing ample perfor-
mance headroom for future growth.
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