Intel i7-980X BX80613I7980X User Manual
Product codes
BX80613I7980X
Datasheet
51
Register Description
2.8.4
MC_SMI_SPARE_CNTRL
System Management Interrupt and Spare control register.
2.8.5
MC_RESET_CONTROL
DIMM Reset enabling controls.
Device:
3
Function: 0
Offset:
54h
Access as a Dword
Bit
Type
Reset
Value
Description
16
RW
0
INTERRUPT_SELECT_NMI
1 = Enable NMI signaling.
0 = Disable NMI signaling.
If both NMI and SMI enable bits are set, then only SMI is sent.
1 = Enable NMI signaling.
0 = Disable NMI signaling.
If both NMI and SMI enable bits are set, then only SMI is sent.
15
RW
0
INTERRUPT_SELECT_SMI
1 = Enable SMI signaling.
0 = Disable SMI signaling.
If both NMI and SMI enable bits are set, then only SMI is sent. This bit functions
1 = Enable SMI signaling.
0 = Disable SMI signaling.
If both NMI and SMI enable bits are set, then only SMI is sent. This bit functions
the same way in Mirror and Independent Modes.
The possible SMI events enabled by this bit are:
Any one of the error counters MC_COR_ECC_CNT_X meets the value of
The possible SMI events enabled by this bit are:
Any one of the error counters MC_COR_ECC_CNT_X meets the value of
SMI_ERROR_THRESHOLD field of this register.
MC_SSRSTATUS.CMPLT bit is set to 1.
MC_RAS_STATUS.REDUNDANCY_LOSS bit is set to 1.
14:0
RW
0
SMI_ERROR_THRESHOLD
Defines the error threshold to compare against the per-DIMM error counters
Defines the error threshold to compare against the per-DIMM error counters
MC_COR_ECC_CNT_X, which are also 15 bits.
Device:
3
Function: 0
Offset:
5Ch
Access as a Dword
Bit
Type
Reset
Value
Description
0
WO
0
BIOS_RESET_ENABLE
When set, MC takes over control of driving RESET to the DIMMs. This bit is set
When set, MC takes over control of driving RESET to the DIMMs. This bit is set
on S3 exit and cold boot to take over RESET driving responsibility from the
physical layer.