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Intel i7-980X BX80613I7980X User Manual

Product codes
BX80613I7980X
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Page of 98
Datasheet
59
Register Description
2.10
Integrated Memory Controller Channel Control 
Registers
2.10.1
MC_CHANNEL_0_DIMM_RESET_CMD
MC_CHANNEL_1_DIMM_RESET_CMD
MC_CHANNEL_2_DIMM_RESET_CMD
Integrated Memory Controller DIMM reset command register. This register is used to 
sequence the reset signals to the DIMMs.
9:8
RW
-
Logical Channel2. 
Index 010 of the Interleave List. Bits determined from the matching 
TAD_DRAM_RULE mode.
00 = Logical channel 0
01 = Logical channel 1
10 = Logical channel 2
11 = Reserved
5:4
RW
-
Logical Channel1. 
Index 001 of the Interleave List. Bits determined from the matching 
TAD_DRAM_RULE mode.
00 = Logical channel 0
01 = Logical channel 1
10 = Logical channel 2
11 = Reserved
1:0
RW
-
Logical Channel0. 
Index 000 of the Interleave List. Bits determined from the matching 
TAD_DRAM_RULE mode.
00 = Logical channel 0
01 = Logical channel 1
10 = Logical channel 2
11 = Reserved
Device:
3
Function: 1
Offset:
C0h, C4h, C8h, CCh, D0h, D4h, D8h, DCh
Access as a Dword
Device:
4, 5, 6
Function: 0
Offset:
50h
Access as a Dword
Bit
Type
Reset
Value
Description
2
RW
0
BLOCK_CKE. 
When set, CKE will be forced to be deasserted.
1
RW
0
ASSERT_RESET. 
When set, Reset will be driven to the DIMMs.
0
WO
0
RESET. 
Reset the DIMMs. Setting this bit will cause the Integrated Memory Controller 
DIMM Reset state machine to sequence through the reset sequence using the 
parameters in MC_DIMM_INIT_PARAMS.