Intel i7-980X BX80613I7980X User Manual

62

Datasheet

The initialization state is stored in this register. This register is cleared on a new 
training command.

9

RO

0

RCOMP_CMPLT. 
When set, indicates that RCOMP command has complete. This bit is cleared by 

hardware on command issuance and set once the command is complete.

8

RO

0

INIT_CMPLT. 
This bit is cleared when a new training command is issued. It is set once the 

sequence is complete regardless of whether all steps passed or not.

7

RO

0

ZQCL_CMPLT. 
When set, indicates that ZQCL command has completed. This bit is cleared by 

hardware on command issuance and set once the command is complete.

6

RO

0

WR_DQ_DQS_PASS. 
Set after a training command when the Write DQ-DQS training step passes. 

The bit is cleared by hardware when a new training command is sent.

5

RO

0

WR_LEVEL_PASS. 
Set after a training command when the write leveling training step passes. The 

bit is cleared by hardware when a new training command is sent.

4

RO

0

RD_RCVEN_PASS. 
Set after a training command when the Read Receive Enable training step 

passes. The bit is cleared by hardware when a new training command is sent. 

3

RO

0

RD_DQ_DQS_PASS. 
Set after a training command when the Read DQ-DQS training step passes. The 

bit is cleared by hardware when a new training command is sent.

2:0

RO

0

PHYFSMSTATE. 
The current state of the top level training FSM. 
000 = IDLE 
001 = RD DQ-DQS 
010 = RcvEn Bitlock 
011 = Write Level 
100 = WR DQ-DQS