Intel E7220 LF80564QH0778M Data Sheet

Document Number: 318080-002

117

Actual implementation may vary. This figure is provided to offer a general understanding of the 

architecture. All SMBus pull-up and pull-down resistors are 10 kΩ and located on the processor.

Of the addresses broadcast across the SMBus, the memory component claims those of 
the form “1010XXXZb”. The “XXX” bits are defined by pull-up and pull-down resistors 
on the system baseboard. These address pins are pulled down weakly (10 kΩ) on the 

processor substrate to ensure that the memory components are in a known state in 
systems which do not support the SMBus (or only support a partial implementation). 
The “Z” bit is the read/write bit for the serial bus transaction.

Note that addresses of the form “0000XXXXb” are Reserved and should not be 
generated by an SMBus master. The system designer must also ensure that their 
particular implementation does not add excessive capacitance to the address inputs. 
Excess capacitance at the address inputs may cause address recognition problems. 
Refer to the appropriate platform design guide document.

 shows a logical diagram of the pin connections. 

 describe the 

address pin connections and how they affect the addressing of the devices.

CLK

DATA