Intel E7220 LF80564QH0778M Data Sheet

Product codes
LF80564QH0778M
Page of 142
Document Number: 318080-002
137
Features
7.4.4
Checksums
 includes the checksum values for 
each section defined in the 128 byte ROM.
Checksums are automatically calculated and programmed by Intel. The first step in 
calculating the checksum is to add each byte from the field to the next subsequent 
byte. This result is then negated to provide the checksum.
Example: For a byte string of AA445Ch, the resulting checksum will be B6h.
AA = 10101010 
44 = 01000100
5C = 0101100
AA + 44 + 5C = 01001010
Negate the sum: 10110101 +1 = 101101 (B6h)
7.4.5
Scratch EEPROM
Also available in the memory component on the processor SMBus is an EEPROM which 
may be used for other data at the system or processor vendor’s discretion. The data in 
this EEPROM, once programmed, can be write-protected by asserting the active-high 
SM_WP signal. This signal has a weak pull-down (10 kΩ) to allow the EEPROM to be 
programmed in systems with no implementation of this signal. The Scratch EEPROM 
resides in the upper half of the memory component (addresses 80 - FFh). The lower 
half comprises the Processor Information ROM (addresses 00 - 7Fh), which is 
permanently write-protected by Intel.
§
Offset:
7Fh
Bit
Description
7:0
Feature Data Checksum
One Byte Checksum of the Feature Data Section
00h- FFh: See 
 for calculation of the value
Table 7-7.
128 Byte ROM Checksum Values
Section
Checksum Address
Header
0Dh
Processor Data 
15h
Processor Core Data
24h
Cache Data
31h
Package Data
37h
Part Number Data 
6Fh
Thermal Ref. Data
73h
Feature Data
7Fh