Intel E7220 LF80564QH0778M Data Sheet

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Document Number: 318080-002

remains within the specifications listed in 

. Failure to do so can result in 

timing violations or reduced lifetime of the component. For further information and 
guidelines, refer to the appropriate platform design guidelines.

Vcc regulator solutions need to provide bulk capacitance with a low Effective Series 
Resistance (ESR). Bulk decoupling must be provided on the baseboard to handle large 
current swings. The power delivery solution must ensure the voltage and current 
specifications are met (as defined in 

). For further information regarding 

power delivery, decoupling and layout guidelines, refer to the appropriate platform 
design guidelines.

Bulk decoupling must be provided on the baseboard. Decoupling solutions must be 
sized to meet the expected load. To ensure optimal performance, various factors 
associated with the power delivery solution must be considered including regulator 
type, power plane and trace sizing, and component placement. A conservative 
decoupling solution consists of a combination of low ESR bulk capacitors and high 
frequency ceramic capacitors. For further information regarding power delivery, 
decoupling and layout guidelines, refer to the appropriate platform design guidelines.

The processor integrates signal termination on the die, as well as a portion of the 
required high frequency decoupling capacitance on the processor package. However, 
additional high frequency capacitance must be added to the baseboard to properly 
decouple the return currents from the FSB. Bulk decoupling must also be provided by 
the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in 
the appropriate platform design guidelines.

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the 
processor. As in previous processor generations, the processor core frequency is a 
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is set during 
manufacturing. The default setting is for the maximum speed of the processor.

The processor core frequency is configured during reset by using values stored 
internally during manufacturing. The stored value sets the highest bus fraction at which 
the particular processor can operate. If lower speeds are desired, the appropriate ratio 
can be configured via the CLOCK_FLEX_MAX Model Specific Register (MSR). 

Clock multiplying within the processor is provided by the internal phase locked loop 
(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread 
spectrum clocking. Processor DC and AC specifications for the BCLK[1:0] inputs are 
provided in 

, respectively. These specifications must be met 

while also meeting signal integrity requirements as outlined in 

. The 

processor utilizes differential clocks.  

 contains processor core frequency to 

FSB multipliers and their corresponding core frequencies.