Intel E7220 LF80564QH0778M Data Sheet

Document Number: 318080-002

87

A[39:3]#

I/O

A[39:3]# (Address) define a 2

40

-byte physical memory address space. In sub-phase 

1 of the address phase, these pins transmit the address of a transaction. In sub-

phase 2, these pins transmit transaction type information. These signals must 

connect the appropriate pins of all agents on the Intel

®

 Xeon

®

 Processor 7200 Series 

and 7300 Series FSB. A[39:3]# are protected by parity signals AP[1:0]#. A[39:3]# 

are source synchronous signals and are latched into the receiving buffers by 

ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processors sample a subset of the 

A[39:3]# pins to determine their power-on configuration. See 

A20M#

I

If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 

(A20#) before looking up a line in any internal cache and before driving a read/write 

transaction on the bus. Asserting A20M# emulates the 8086 processor's address 

wrap-around at the 1 MB boundary. Assertion of A20M# is only supported in real 

mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal 

following an I/O write instruction, it must be valid along with the TRDY# assertion of 

the corresponding I/O write bus transaction. 

ADS#

I/O

ADS# (Address Strobe) is asserted to indicate the validity of the transaction address 

on the A[39:3]# pins. All bus agents observe the ADS# activation to begin parity 

checking, protocol checking, address decode, internal snoop, or deferred reply ID 

match operations associated with the new transaction. This signal must be connected 

to the appropriate pins on all Intel

®

 Xeon

®

 Processor 7200 Series and 7300 Series 

FSB agents.

ADSTB[1:0]#

I/O

Address strobes are used to latch A[39:3]# and REQ[4:0]# on their rising and falling 

edge. Strobes are associated with signals as shown below.

AP[1:0]#

I/O

AP[1:0]# (Address Parity) are driven by the requestor one common clock after 

ADS#, A[39:3]#, REQ[4:0]# are driven. A correct parity signal is electrically high if 

an even number of covered signals are electrically low and electrically low if an odd 

number of covered signals are electrically low. This allows parity to be electrically 

high when all the covered signals are electrically high. AP[1:0]# should connect the 

appropriate pins of all Intel

®

 Xeon

®

 Processor 7200 Series and 7300 Series FSB 

agents. The following table defines the coverage for these signals.

BCLK[1:0]

I

The differential bus clock pair BCLK[1:0] (Bus Clock) determines the FSB frequency. 

All processor FSB agents must receive these signals to drive their outputs and latch 

their inputs.
All external timing parameters are specified with respect to the rising edge of BCLK0 

crossing V

CROSS

.

REQ[4:0], 

A[37:36,16:3]#

ADSTB0#

A[39:38, 35:17]#

ADSTB1#

A[39:24]#

AP0#

AP1#

A[23:3]#

AP1#

AP0#

REQ[4:0]#

AP1#

AP0#