Intel SL2YM User Manual
Pentium
®
II Processor at 350 MHz, 400 MHz, and 450 MHz
14
Datasheet
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior.
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior.
2.2.7
Clock Control
The processor provides the clock signal to the L2 cache. During AutoHALT Power Down and
Stop-Grant states, the processor will process a system bus snoop. The processor will not stop the
clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into the Halt/
Grant Snoop state will allow the L2 cache to be snooped, similar to the Normal state.
Stop-Grant states, the processor will process a system bus snoop. The processor will not stop the
clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into the Halt/
Grant Snoop state will allow the L2 cache to be snooped, similar to the Normal state.
When the processor is in Sleep and Deep Sleep states, it will not respond to interrupts or snoop
transactions. During the Sleep state, the clock to the L2 cache is not stopped. During the Deep
Sleep state, the clock to the L2 cache is stopped. The clock to the L2 cache will be restarted only
after the internal clocking mechanism for the processor is stable (i.e., the processor has re-entered
Sleep state).
transactions. During the Sleep state, the clock to the L2 cache is not stopped. During the Deep
Sleep state, the clock to the L2 cache is stopped. The clock to the L2 cache will be restarted only
after the internal clocking mechanism for the processor is stable (i.e., the processor has re-entered
Sleep state).
PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.
PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep
Sleep state to the Sleep state, PICCLK must be restarted with BCLK.
PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep
Sleep state to the Sleep state, PICCLK must be restarted with BCLK.
2.3
Power and Ground Pins
The operating voltage of the processor die and of the L2 cache die differ from each other. There are
two groups of power inputs on the Pentium II processor package to support this voltage difference
between the components in the package. There are also five pins defined on the package for voltage
identification (VID). These pins specify the voltage required by the processor core. These have
been added to cleanly support voltage specification variations on current and future Pentium II
processors.
two groups of power inputs on the Pentium II processor package to support this voltage difference
between the components in the package. There are also five pins defined on the package for voltage
identification (VID). These pins specify the voltage required by the processor core. These have
been added to cleanly support voltage specification variations on current and future Pentium II
processors.
For clean on-chip power distribution, Pentium II processors have 27 V
CC
(power) and 30 V
SS
(ground) inputs. The 27 V
CC
pins are further divided to provide the different voltage levels to the
components. V
CC
CORE
inputs for the processor core and some L2 cache components account for 19
of the V
CC
pins, while 4 V
TT
inputs (1.5 V) are used to provide an AGTL+ termination voltage to
the processor and 3 V
CC
L2
inputs (3.3 V) are for use by the L2 cache TagRAM and BSRAMs. One
V
CC5
pin is provided for use by the Slot 1 Test Kit. V
CC5
, V
CCL2
, and V
CC
CORE
must remain electrically
separated from each other. On the circuit board, all V
CC
CORE
pins must be connected to a voltage
island and all V
CCL2
pins must be connected to a separate voltage island (an island is a portion of a
power plane that has been divided, or an entire plane). Similarly, all V
SS
pins must be connected to
a system ground plane.
2.4
Decoupling Guidelines
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. This causes voltages on
power planes to sag below their nominal values if bulk decoupling is not adequate. Care must be
taken in the board design to ensure that the voltage provided to the processor remains within the
specifications listed in
generating large average current swings between low and full power states. This causes voltages on
power planes to sag below their nominal values if bulk decoupling is not adequate. Care must be
taken in the board design to ensure that the voltage provided to the processor remains within the
specifications listed in
Table 5
. Failure to do so can result in timing violations or a reduced lifetime
of the component.