Intel Pentium 4 (551) JM80547PG0961M User Manual
Product codes
JM80547PG0961M
Intel
®
Pentium
®
4 Processor in the 423-pin Package
21
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
4. V
OH
may experience excursions above V
CC
. However, input signal drivers must comply with the signal quality
specifications in Chapter 3.0.
5. Refer to processor I/O Buffer Models for I/V characteristics.
6. The V
6. The V
CC
referred to in these specifications is the instantaneous V
CC
.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Parameter will be measured at 9mA (for use with system inputs).
3. All outputs are open-drain.
4. V
2. Parameter will be measured at 9mA (for use with system inputs).
3. All outputs are open-drain.
4. V
IH
and V
OH
may experience excursions above V
CC
. However, input signal drivers must comply with the
signal quality specifications in Chapter 3.0.
5. The V
CC
referred to in these specifications is the instantaneous V
CC
.
6. These specifications apply to the asynchronous GTL+ signal group.
7. These specifications apply to the TAP signal group.
7. These specifications apply to the TAP signal group.
2.11
AGTL+ System Bus Specifications
Routing topology recommendations may be found in the Intel
®
Pentium
®
4 Processor and Intel
®
850 Chipset Platform Design Guide. Termination resistors are not required for most AGTL+
signals, as these are integrated into the processor silicon.
signals, as these are integrated into the processor silicon.
Valid high and low levels are determined by the input buffers which compare a signal’s voltage
with a reference voltage called GTLREF (known as V
with a reference voltage called GTLREF (known as V
REF
in previous documentation).
Table 9 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be
generated on the system board using high precision voltage divider circuits. It is important that the
system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance
for the AGTL+ signal group traces is known and well-controlled. For more details on platform
design see the Intel
generated on the system board using high precision voltage divider circuits. It is important that the
system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance
for the AGTL+ signal group traces is known and well-controlled. For more details on platform
design see the Intel
®
Pentium
®
4 Processor and Intel
®
850 Chipset Platform Design Guide.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Table 8. Asynchronous GTL+ and TAP Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1
V
IL
Input Low Voltage
-0.150
GTLREF - 100mV
V
5
V
IL
Input Low Voltage
-0.150
V
CC
/2 - 0.30
V
IH
Input High Voltage
GTLREF + 100mV
V
CC
V
4, 5
V
IH
Input High Voltage
V
CC
/2 + 0.30
V
CC
V
OH
Output High Voltage
V
CC
V
3, 4, 5
I
OL
Output Low Current
56
mA
6
I
LI
Input Leakage Current
± 100
µA
I
LO
Output Leakage Current
± 100
µA
Table 9. AGTL+ Bus Voltage Definitions
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
GTLREF
Bus Reference Voltage
-2%
2/3 V
CC
+2%
V
2, 3, 6
R
TT
Termination Resistance
36
41
46
Ω
4
COMP[1:0]
COMP Resistance
42.77
43.2
45.45
Ω
5, 7