Intel Pentium 4 (551) JM80547PG0961M User Manual
Product codes
JM80547PG0961M
Intel
®
Pentium
®
4 Processor in the 423-pin Package
28
Figure 7. System Bus Reset and Configuration Timings
Figure 8. Source Synchronous 2X (Address) Timings
BCLK[1:0]1
T
y
Safe
Valid
T
z
Valid
T
v
T
w
T
x
T
u
T
t
BCLK
RESET#
Configuration
(A20M#, IGNNE#,
LINT[1:0])
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
T
t
= T9 (GTL+ Input Hold Time)
T
u
= T8 (GTL+ Input Setup Time)
T
v
= T10 (RESET# Pulse Width)
T
w
= T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
T
x
= T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
Ty = T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time)
Tz = T18 (Reset Configuration Signals (A20M# IGNNE# LINT[1:0]) Setup Time)
Tz = T18 (Reset Configuration Signals (A20M# IGNNE# LINT[1:0]) Setup Time)
T
v
= T13 (RESET# Pulse Width)
T
w
= T45 (Reset Configuration Signals Setup Time)
T
x
= T46 (Reset Configuration Signals Hold Time)
(A[31:3], BR0#,
INIT#, SMI#)
INIT#, SMI#)
T
J
BCLK0
BCLK1
ADSTB# (@ driver)
A# (@ driver)
A# (@ receiver)
ADSTB# (@ receiver)
T1
T2
2.5 ns
5.0 ns
7.5 ns
T
H
T
H
T
J
T
N
T
K
T
M
valid
valid
valid
valid
T
H
= T23: Source Sync. Address Output Valid Before Address Strobe
T
J
= T24: Source Sync. Address Output Valid After Address Strobe
T
K
= T27: Source Sync. Input Setup to BCLK
T
M
= T26: Source Sync. Input Hold Time
T
N
= T25: Source Sync. Input Setup Time
T
P
= T28: First Address Strobe to Second Address Strobe
T
S
= T20: Source Sync. Output Valid Delay
T
R
= T31: Address Strobe Output Valid Delay
T
P
T
R
T
S