Intel X3360 AT80569KJ073N Data Sheet
Product codes
AT80569KJ073N
Datasheet
19
Electrical Specifications
different settings within the VID range. Note that this differs from the VID employed by the
processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep
processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep
®
Technology, or Extended HALT State).
2.
Unless otherwise noted, all specifications in this table are based on estimates and
simulations or empirical data. These specifications will be updated with characterized data
from silicon measurements at a later date.
simulations or empirical data. These specifications will be updated with characterized data
from silicon measurements at a later date.
3.
These voltages are targets only. A variable voltage source should exist on systems in the
event that a different voltage is required. See
event that a different voltage is required. See
and Table 2-1 for more
information.
4.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE
lands at the socket with a 100MHz bandwidth oscilloscope, 1.5 pF maximum probe
capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into
the oscilloscope probe.
lands at the socket with a 100MHz bandwidth oscilloscope, 1.5 pF maximum probe
capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into
the oscilloscope probe.
5.
Refer to
and
for the minimum, typical, and maximum V
CC
allowed for
a given current. The processor should not be subjected to any V
CC
and I
CC
combination
wherein V
CC
exceeds V
CC_MAX
for a given current.
6.
FMB is the Flexible Motherboard guideline. These guidelines are for estimation purposes
only. See
only. See
for further details on FMB guidelines.
7.
I
CC_MAX
specification is based on V
CC_
MAX
loadline. Refer to
for details.
8.
V
TT
must be provided via a separate voltage source and not be connected to V
CC
. This
specification is measured at the land.
9.
Baseboard bandwidth is limited to 20 MHz.
10.
This is the maximum total current drawn from the V
TT
plane by only the processor. This
specification does not include the current coming from on-board termination (R
TT
),
through the signal line. Refer to the appropriate platform design guide and the Voltage
Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket to determine the total I
Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket to determine the total I
TT
drawn by the system. This parameter is based on
design characterization and is not tested.
11.
Adherence to the voltage specifications for the processor are required to ensure reliable
processor operation.
processor operation.
Table 2-4.
V
CC
Static and Transient Tolerance
I
CC
(A)
Voltage Deviation from VID Setting (V)
1, 2, 3, 4
Maximum Voltage
1.30 mΩ
Typical Voltage
1.38 mΩ
Minimum Voltage
1.45 mΩ
0
0.000
-0.019
-0.038
5
-0.007
-0.026
-0.045
10
-0.013
-0.033
-0.053
15
-0.020
-0.040
-0.060
20
-0.026
-0.047
-0.067
25
-0.033
-0.053
-0.074
30
-0.039
-0.060
-0.082
35
-0.046
-0.067
-0.089
40
-0.052
-0.074
-0.096
45
-0.059
-0.081
-0.103
50
-0.065
-0.088
-0.111
55
-0.072
-0.095
-0.118
60
-0.078
-0.102
-0.125
65
-0.085
-0.108
-0.132
70
-0.091
-0.115
-0.140
75
-0.098
-0.122
-0.147
80
-0.101
-0.126
-0.151