Intel X3360 AT80569KJ073N Data Sheet
Product codes
AT80569KJ073N
Electrical Specifications
30
Datasheet
2.9.4
BCLK[1:0] Specifications
NOTES:
1.
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Crossing voltage is defined as the instantaneous voltage value when the rising edge of
BCLK0 equals the falling edge of BCLK1.
BCLK0 equals the falling edge of BCLK1.
3.
“Steady state” voltage, not including overshoot or undershoot.
4.
Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined
as the absolute value of the minimum voltage.
as the absolute value of the minimum voltage.
5.
Measurement taken from differential waveform.
NOTES:
1.
1.
Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 333 MHz BCLK[1:0].
frequencies based on a 333 MHz BCLK[1:0].
2.
The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). Min period specification
is based on -300 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +300 PPM deviation from a 3 ns period and a +0.5% maximum variance
due to spread spectrum clocking.
specification as governed by the period stability specification (T2). Min period specification
is based on -300 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +300 PPM deviation from a 3 ns period and a +0.5% maximum variance
due to spread spectrum clocking.
3.
For the clock jitter specification, refer to the CK505 Clock Synthesizer Specification.
4.
In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
5.
Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.
Measurement taken from differential waveform.
6.
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
measured using a ±75mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
Table 2-16. Front Side Bus Differential BCLK Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes
1
V
L
Input Low Voltage
-0.30
N/A
N/A
V
3
V
H
Input High Voltage
N/A
N/A
1.15
V
3
V
CROSS(abs)
Absolute Crossing
Point
Point
0.300
N/A
0.550
V
2
∆V
CROSS
Range of Crossing
Points
Points
N/A
N/A
0.140
V
-
V
OS
Overshoot
N/A
N/A
1.4
V
4
V
US
Undershoot
-0.300 N/A
N/A
V
4
V
SWING
Differential Output
Swing
Swing
0.300
N/A
N/A
V
5
Table 2-17. FSB Differential Clock Specifications (1333 MHz FSB)
T# Parameter
Min
Nom
Max
Unit
Figure Notes
1
BCLK[1:0] Frequency
331.633
-
333.367
MHz
-
7
T1: BCLK[1:0] Period
2.99970
-
3.01538
ns
2
T2: BCLK[1:0] Period Stability
-
-
150
ps
3, 4
T5: BCLK[1:0] Rise and Fall Slew
Rate
Rate
2.5
-
8
V/ns
5
Slew Rate Matching
N/A
N/A
20
%
-
6