Intel X3360 AT80569KJ073N Data Sheet

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Datasheet

The processor will respond to snoop transactions on the FSB while in Stop-Grant state 

or in HALT Power Down state. During a snoop transaction, the processor enters the 

HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the 

snoop on the FSB has been serviced (whether by the processor or another agent on the 

FSB). After the snoop is serviced, the processor will return to the Stop Grant state or 

HALT Power Down state, as appropriate.

The Extended HALT Snoop State is the default Snoop State when the Extended HALT 

state is enabled via the BIOS. The processor will remain in the lower bus ratio and VID 

operating point of the Extended HALT state.

While in the Extended HALT Snoop State, snoops are handled the same way as in the 

HALT Snoop State. After the snoop is serviced the processor will return to the Extended 

HALT state.

The processor supports Enhanced Intel SpeedStep Technology. This technology enables 

the processor to switch between frequency and voltage points, which may result in 

platform power savings. In order to support this technology, the system must support 

dynamic VID transitions. Switching between voltage/frequency states is software 

controlled. 

Enhanced Intel SpeedStep Technology is a technology that creates processor 

performance states (P states). P states are power consumption and capability states 

within the Normal state as shown in 

. Enhanced Intel SpeedStep Technology 

enables real-time dynamic switching between frequency and voltage points. It alters 

the performance of the processor by changing the bus to core frequency ratio and 

voltage. This allows the processor to run at different core frequencies and voltages to 

best serve the performance and power requirements of the processor and system. Note 

that the front side bus is not altered; only the internal core frequency is changed. In 

order to run at reduced power consumption, the voltage is altered in step with the bus 

ratio. 

The following are key features of Enhanced Intel SpeedStep Technology:

• Voltage/Frequency selection is software controlled by writing to processor MSR's 

(Model Specific Registers), thus eliminating chipset dependency.
- If the target frequency is higher than the current frequency, Vcc is incremented in 

steps (+12.5 mV) by placing a new value on the VID signals after which the 

processor shifts to the new frequency. Note that the top frequency for the 

processor can not be exceeded.
- If the target frequency is lower than the current frequency, the processor shifts to 

the new frequency and Vcc is then decremented in steps (-12.5 mV) by changing 

the target VID through the VID signals.

The processor incorporates the PSI# signal that is asserted when the processor is in a 
reduced power consumption state. PSI# can be used to improve efficiency of the 
voltage regulator, resulting in platform power savings. For details, refer to the 
compatible chipset Platform Design Guide and Voltage Regulator-Down (VRD) 11.1 
Processor Power Delivery Design Guidelines.

PSI# may be asserted only when the processor is in the Deeper Sleep state.