Panasonic SJ-MJ88 User Manual

Page of 62
Pin 
No.
Mark
I/O 
Division
Function
1
RVDD 3
I
Power supply to internal 
DRAM
2
RVDD 18
O
Voltage regulator output 
terminal (Connects to 
internal DRAM supply 
terminal)
3
RVDD 23
Voltage regulator input 
terminal (Accepts a supply 
voltage identical to that for 
IO pad)
4
LON
I
Voltage regulator ON/OFF 
control signal input 
terminal (1:ON, 2:OFF)
5
TMDISY
O
Microprocessor interrupt 
signal 3 output terminal 
(for monitoring)
6
TSGSY 
NC
O
ATRAC frame sync. signal 
output terminal (for 
monitoring)
7
MONI6
O
Monitor signal output 
terminal 6
8
MONI5
O
Monitor signal output 
terminal 5
9
NRST
I
Chip Reset signal input 
terminal (O:reset)
10
SELAD
I
Microprocessor IF address 
data select signal input 
terminal
11
SSCK
I
Microprocessor IF shift 
clock signal input terminal
12
SSDW
I
Microprocessor IF write 
data input terminal
13
SSDR
O
Microprocessor IF read 
data output terminal
14
NRQ
O
Microprocessor interrupt 
signal 1 output terminal
15
MDAS 
CSY
O
Microprocessor interrupt 
signal 2 output terminal
16
FG
I
FG input terminal
17
TRDP
O
Tracking drive (+) PWM 
signal output terminal
18
TRDM
O
Tracking drive (-) PWM 
signal output terminal
46