Hynix HMP125U6EFR8C-S6 Leaflet

Rev. 0.3 / Nov. 2008 6

240pin DDR2 SDRAM Unbuffered DIMMs

FUNCTIONAL BLOCK DIAGRAM
512MB(64Mbx64): HMP164U6EFR6C

/ S 0

/ D Q S 0

D M 0

D Q S 0

D 0

D Q 0

I/ O 0

D Q 1

I/ O 1

D Q 2

I/ O 2

D Q 3

I/ O 3

D Q 4

I/ O 4

D Q 5

I/ O 5

D Q 6

I/ O 6

I/ O 7

D Q 7

/ D Q S 1

D M 1

D Q S 1

D Q 8

D Q 9

D Q 10

D Q 11

D Q 12

D Q 13

D Q 14

D Q 15

/ C S

/ LD Q S

LD Q S

LD M

D Q 16

D Q 17

D Q 18

D Q 19

D Q 20

D Q 21

D Q 22

D Q 23

D Q 24

D Q 25

D Q 26

D Q 27

D Q 28

D Q 29

D Q 30

D Q 31

/ D Q S 2

D M 2

D Q S 2

D 1

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

/ D Q S 3

D M 3

D Q S 3

/ C S

/ L D Q S

L D Q S

LD M

/ D Q S 4

D M 4

D Q S 4

D Q 32

D Q 33

D Q 34

D Q 35

D Q 36

D Q 37

D Q 38

D Q 39

/ D Q S 5

D M 5

D Q S 5

D 2

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

/ C S

/ L D Q S

L D Q S

LD M

D Q 40

D Q 41

D Q 42

D Q 43

D Q 44

D Q 45

D Q 46

D Q 47

/ D Q S 7

D M 7

D Q S 7

D Q 56

D Q 57

D Q 58

D Q 59

D Q 60

D Q 61

D Q 62

D Q 63

D 3

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

/ C S

/ L D Q S

L D Q S

LD M

D Q 48

D Q 49

D Q 50

D Q 51

D Q 52

D Q 53

D Q 54

D Q 55

/ D Q S 6

D M 6

D Q S 6

B A 0 - B A 2

A 0 - A 12

/ R A S

/ C A S

S D R A M S D0-D 3

C K E 0

/ W E

O D T 0

I/ O 8

I/ O 9

I/ O 10

I/ O 11

I/ O 12

I/ O 13

I/ O 14

I/ O 15

/ U D Q S

U D Q S

U D M

I/ O 8

I/ O 9

I/ O 10

I/ O 11

I/ O 12

I/ O 13

I/ O 14

I/ O 15

/ U D Q S

U D Q S

U D M

I/ O 8

I/ O 9

I/ O 10
I/ O 11

I/ O 12

I/ O 13

I/ O 14

I/ O 15

/ U D Q S

U D Q S

U D M

I/ O 8

I/ O 9

I/ O 10

I/ O 11

I/ O 12

I/ O 13

I/ O 14

I/ O 15

/ U D Q S

U D Q S

U D M

S D R A M S D0-D 3

S D R A M S D0-D 3
S D R A M S D0-D 3

S D R A M S   D0-D 3
S D R A M S   D0-D 3
S D R A M S   D0-D 3

VD D SPD

V REF

VD D/ V DD Q

VSS

S erial P D

D O -D 3

N otes :
1. D Q ,D M ,D Q S ,/D Q S resistors : 22 Ω +/- 5 % .
2. B ax,A x,/R A S ,/C A S ,/W E resistors : 10 Ω +/- 5 % .

S C L

S D A

W P

S e rial P D

S C L

S A0

S A1

S A2

C lo ck S ig n al L o ad s

C K 0, /C K 0

C K 1, /C K 1

N C

C K 2, /C K 2

C lock Input

S D R A M s