Intel E5640 AT80614005466AA User Manual

20

• 210  each  V

CC

 (271 ea. V

SS

) lands must be supplied with the voltage determined by 

the VID[7:0] signals. 

 defines the voltage level associated with each core 

VID pattern. 

 represent V

CC 

static and transient limits.

• 3  each  V

CCPLL

 lands, connected to a 1.8 V supply, power the Phase Lock Loop (PLL) 

clock generation circuitry. An on-die PLL filter solution is implemented within the 
processor.

• 45 each V

DDQ

 (17 ea. V

SS

) lands, connected to a 1.50 / 1.35 V supply, provide 

power to the processor DDR3 interface. This supply also powers the DDR3 memory 
subsystem.

• 7  each  V

TTA

 (5 ea. V

SS

) and 26 ea. V

TTD

 (17 ea. V

SS

) lands must be supplied with 

the voltage determined by the VTT_VID[4:2] signals. Coupled with a 20 mV offset, 
this corresponds to a VTT_VID pattern of ‘010xxx10’. 

 specifies the 

voltage levels associated with each VTT

_

VID pattern. 

 and 

represent V

TT 

static and transient limits.

All V

CC

, V

CCPLL, 

V

DDQ, 

V

TTA

, and V

TTD

 lands must be connected to their respective 

processor power planes, while all V

SS

 lands must be connected to the system ground 

plane. 

Due to its large number of transistors and high internal clock speeds, the processor is 
capable of generating large current swings between low and full power states. This may 
cause voltages on power planes to sag below their minimum values if bulk decoupling is 
not adequate. Larger bulk storage (C

BULK

), such as electrolytic capacitors, supply 

current during longer lasting changes in current demand, for example coming out of an 
idle condition. Similarly, they act as a storage well for current when entering an idle 
condition from a running condition. Care must be taken in the baseboard design to 
ensure that the voltages provided to the processor remain within the specifications 
listed in 

. Failure to do so can result in timing violations or reduced lifetime of 

the processor. 

The voltage set by the VID signals is the maximum reference voltage regulator (VR) 
output to be delivered to the processor V

CC

 lands. VID signals are CMOS push/pull 

outputs. Please refer to 

 for the DC specifications for these signals.

Individual processor VID values may be calibrated during manufacturing such that two 
devices at the same core frequency may have different default VID settings.

The processor uses eight voltage identification signals, VID[7:0], to support automatic 
selection of power supply voltages. 

 specifies the voltage level corresponding 

to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers 
to a low voltage level. If the processor socket is empty (SKTOCC# pulled high), or the 
voltage regulation circuit cannot supply the voltage that is requested, the voltage 
regulator must disable itself. 

The processor provides the ability to operate while transitioning to an adjacent VID and 
its associated processor core voltage (V

CC

). This is represented by a DC shift in the 

loadline. It should be noted that a low-to-high or high-to-low voltage state change may 
result in as many VID transitions as necessary to reach the target core voltage. 
Transitions above the maximum specified VID are not permitted. 

 includes VID 

step sizes and DC shift ranges. Minimum and maximum voltages must be maintained 
as shown in 

.