Intel E5640 AT80614005466AA User Manual

25

1.

When the “11111111” VID pattern is observed, or when the SKTOCC# pin is pulled high, the voltage 

regulator output should be disabled.

2.

The VID range includes VID transitions that may be initiated by thermal events, Extended HALT state 

transitions (see 

), higher C-States (see 

) or Enhanced Intel SpeedStep

®

 Technology 

transitions (see 

3.

Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a 

specific VID off code is received, the VRM/EVRD must turn off its output (the output should go to high 

impedance) within 500 ms and latch off until power is cycled.

VID[7:0] signals also serve a second function. During power-up, Power-On 
Configuration POC[7:0] logic levels are MUX’ed onto these signals via 1-5 kΩ pull-up or 

pull down resistors located on the baseboard. These values provide voltage regulator 
keying (VID[7]), inform the processor of the platforms power delivery capabilities 
(MSID[2:0]), and program the gain applied to the ISENSE input (CSC[2:0]). 

 

maps VID signals to the corresponding POC functionality.

1

0

1

0

0

0

1

0

0.60000

1

0

1

0

0

0

1

1

0.59375

1

0

1

0

0

1

0

0

0.58750

1

0

1

0

0

1

0

1

0.58125

1

0

1

0

0

1

1

0

0.57500

1

0

1

0

0

1

1

1

0.56875

1

0

1

0

1

0

0

0

0.56250

1

0

1

0

1

0

0

1

0.55625

1

0

1

0

1

0

1

0

0.55000

1

0

1

0

1

0

1

1

0.54375

1

0

1

0

1

1

0

0

0.53750

1

0

1

0

1

1

0

1

0.53125

1

0

1

0

1

1

1

0

0.52500

1

0

1

0

1

1

1

1

0.51875

1

0

1

1

0

0

0

0

0.51250

1

0

1

1

0

0

0

1

0.50625

1

0

1

1

0

0

1

0

0.50000

1

1

1

1

1

1

1

0

OFF

1

1

1

1

1

1

1

1

OFF

VR_Key

VID[7]

0b for VR11.1

Electronic safety key 

distinguishing VR11.1

Spare

VID[6]

0b (default)

Reserved for future use