Silicon Image 141B User Manual
Subject to Change without Notice
SiI 141B PanelLink
®
Digital
Receiver
May
2001
General Description
Features
The SiI 141B uses PanelLink Digital technology to support displays
ranging from VGA to High Refresh XGA (25-86 MHz), which is ideal for LCD
desktop monitor applications. With a flexible single or dual pixel out interface
and selectable output drive, the SiI 141B receiver supports up to true color
panels (24 bit/pixel, 16.7M colors) in 1 pixel/clock mode (18 bit/pixel in 2
pixel/clock mode). PanelLink also features an inter-pair skew tolerance up to
1 full input clock cycle. The SiI 141B is pin for pin compatible with the SiI
141 but incorporates a number of enhancements. These include an
improved jitter tolerant PLL design, new HSYNC filter and power down when
the clock is inactive. All PanelLink products are designed on a scaleable
CMOS architecture to support future performance requirements while
maintaining the same logical interface. System designers can be assured
that the interface will be fixed through a number of technology and
performance generations.
desktop monitor applications. With a flexible single or dual pixel out interface
and selectable output drive, the SiI 141B receiver supports up to true color
panels (24 bit/pixel, 16.7M colors) in 1 pixel/clock mode (18 bit/pixel in 2
pixel/clock mode). PanelLink also features an inter-pair skew tolerance up to
1 full input clock cycle. The SiI 141B is pin for pin compatible with the SiI
141 but incorporates a number of enhancements. These include an
improved jitter tolerant PLL design, new HSYNC filter and power down when
the clock is inactive. All PanelLink products are designed on a scaleable
CMOS architecture to support future performance requirements while
maintaining the same logical interface. System designers can be assured
that the interface will be fixed through a number of technology and
performance generations.
PanelLink Digital technology simplifies PC design by resolving many of
the system level issues associated with high-speed digital design, providing
the system designer with a digital interface solution that is quicker to market
and lower in cost.
the system designer with a digital interface solution that is quicker to market
and lower in cost.
•
Scaleable Bandwidth: 25-86 MHz (VGA to High
Refresh XGA)
Refresh XGA)
•
Low Power: 3.3V core operation & power-down mode
•
Automatic power down when clock is inactive
•
High Skew Tolerance: 1 full input clock cycle (15ns at
65 MHz)
65 MHz)
•
Pin-compatible with Si
I 101, SiI 141
•
Sync Detect: for Plug & Display “Hot Plugging”
•
Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
fiber-optics ready
•
Compliant with DVI 1.0 (DVI is backwards compatible
with VESA® P&D
with VESA® P&D
TM
and DFP)
SiI 141B Pin Diagram
1
SiI141B
80-Pin TQFP
(Top View)
PD
2
PDO
3
OGND
4
PIXS
5
DFO
6
SCDT
7
CTL1
8
CTL2
9
CTL3
10
GND
11
HSYNC
12
OGND
13
VSYNC
14
OVCC
15
Q0
16
Q5
21
Q6
22
Q7
23
Q8
24
Q9
25
OGND
26
Q10
27
OVCC
28
Q11
29
Q12
30
Q13
31
Q14
32
Q15
33
Q16
34
Q17
35
56
Q30
55
Q29
54
Q28
53
Q27
52
Q26
51
VCC
50
Q25
49
OVCC
48
Q24
47
OGND
46
Q23
45
Q22
44
Q21
43
Q20
42
DE
41
Q31
OCK_INV
80
ST
79
PGND
78
PVCC
77
EXT_RES
76
HSYNC_DEJTR
75
RXC+
74
RXC-
73
AGND
72
RX0-
71
RX0+
70
AVCC
69
RX1-
68
RX1+
67
AGND
66
RX2-
65
8-bit Channel 0 Data
1-pixel/clock
24-bit Input Data for 1-pixel/clock mode
DIFFERENTIAL SIGNAL
ODCK
36
8-bit Channel 1 Data
1-pixel/clock
MISC.
GENERAL
PURPOSE
CONTROL
CONTROL
Q1
17
Q2
18
Q3
19
Q4
20
GND
37
Q18
38
VCC
39
Q19
40
60
Q34
59
Q33
58
Q32
57
Q35
RX2+
64
AVCC
63
GND
62
VCC
61
8-bit Channel 2 Data
1-pixel/clock
6-bit Even Channel 0
Data 2-pixel/clock
6-bit Even Channel 2
Data 2-pixel/clock
6-bit Even Channel 1
Data 2-pixel/clock
6-bit Odd Channel 0
Data 2-pixel/clock
6-bit Odd Channel 1
Data 2-pixel/clock
6-bit Odd Channel 2
Data 2-pixel/clock
18-bit Even Data for 2-pixel/clock mode
18-bit Odd Data for 2-pixel/clock mode
RESERVED