Intel E5645 AT80614003597AC User Manual

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• Processors must share symmetry across physical packages with respect to the 

number of logical processors per package, number of cores per package (but not 
necessarily the same subset of cores within the packages), number of Intel 
QuickPath Interconnect interfaces and cache topology.

• Mixing steppings is only supported with processors that have identical Extended 

Family, Extended Model, Processor Type, Family Code and Model Number as 
indicated by the Function 1 of the CPUID instruction. Mixing processors of different 
steppings, but the same mode (as per CPUID instruction) is supported. Details 
regarding the CPUID instruction are provide in the Intel

Architectures Software Developer’s Manual, Volume 2A.

• After AND’ing the feature flag and extended feature flags from the installed 

processors, any processor whose set of feature flags exactly matches the AND’ed 
feature flags can be selected by the BIOS as the BSP. If no processor exactly 
matches the AND’ed feature flag values, then the processor with the numerically 
lower CPUID should be selected as the BSP.

• Intel requires that the proper microcode update be loaded on each processor 

operating within the system. Any processor that does not have the proper 
microcode update loaded is considered by Intel to be operating out-of-specification.

• Customers are fully responsible for the validation of their system configurations

Processors within a system must operate at the same frequency per bits [15:8] of the 

FLEX_RATIO MSR (Address: 194h); however this does not apply to frequency 

transitions initiated due to thermal events, Extended HALT, Enhanced Intel SpeedStep 

Technology transitions signal (See 

The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the 
processor will have over certain time periods. The values are only estimates and actual 
specifications for future processors may differ. Processors may or may not have 
specifications equal to the FMB value in the foreseeable future. System designers 
should meet the FMB values to ensure their systems will be compatible with future 
processors.

 specifies absolute maximum and minimum ratings only, which lie outside the 

functional limits of the processor. Only within specified operation limits, can 
functionality and long-term reliability be expected.

At conditions outside functional operation condition limits, but within absolute 
maximum and minimum ratings, neither functionality nor long-term reliability can be 
expected. If a device is returned to conditions within functional operation limits after 
having been subjected to conditions outside these limits, but within the absolute 
maximum and minimum ratings, the device may be functional, but with its lifetime 
degraded depending on exposure to conditions exceeding the functional operation 
condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality 
nor long-term reliability can be expected. Moreover, if a device is subjected to these 
conditions for any length of time then, when returned to conditions within the 
functional operating condition limits, it will either not function or its reliability will be 
severely degraded.