Intel E5645 AT80614003597AC User Manual
Product codes
AT80614003597AC
Electrical Specifications
44
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
The V
TTA
referred to in these specifications refers to instantaneous V
TTA
.
3.
R
SYS_TERM
is the termination on the system and is not controlled by the processor.
4.
Applies to all Processor Sideband signals, unless otherwise mentioned in
.
5.
This specification only applies to DDR_THERM# and DDR_THERM2#signals.
6.
COMP resistance must be provided on the system board with 1% resistors. COMP0 resistors are tied to V
SS
.
2.7
Intel QuickPath Interconnect Specifications
Intel
QuickPath Interconnect specifications are defined at the processor
pins. In most cases, termination resistors are not required as these are integrated into
the processor silicon (Refer to
the processor silicon (Refer to
).
V
OL
Output Low Voltage
V
TTA
* R
ON
/
(R
ON
+ R
SYS_TERM
)
V
2,3
V
OH
Output High Voltage
V
TTA
V
2
ODT
On-Die Termination
45
55
4
R
ON
Buffer On Resistance for
Processor Sideband Signals
10
18
Ω
R
ON
Buffer On Resistance for
VID[7:0] Signals
100
Ω
I
LI
Input Leakage Current for
Processor Sideband Signals
± 200
μA
I
LI
Input Leakage Current for
DDR_THERM# and
DDR_THERM2# Signals
± 50
μA
5
COMP0
COMP Resistance
49.4
49.9
50.4
Ω
6
Table 2-18. Processor Sideband Signal Group DC Specifications (Sheet 2 of 2)
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
Table 2-19. Common Intel QuickPath Interconnect Specifications (Sheet 1 of 2)
Symbol
Parameter
Min
Nom
Max
Unit
Notes
UIavg
Avg UI size at “f” GT/s
(f = 4.8, 5.86, or 6.4)
0.999 *
Nom
1000/f
1.001 *
Nom
psec
T
slew-rise-fall-pin
Defined as the slope of the rising or
falling waveform as measured between
+/- 100 mV of the differential transmitter
output, for any data or clock.
10
25
V / nsec
Z
TX_LOW_CM_DC
DC resistance of Tx terminations at half
the single ended swing (usually
0.25*V
Tx-diff-pp-pin
) bias point
38
52
Ω
ΔZ
TX_LOW_CM_DC
Defined as: ± (max(Z
TX_LOW_CM_DC
) -
min(Z
TX_LOW_CM_DC
))
/ Z
TX_LOW_CM_DC
expressed in %, over full range of Tx
single ended voltage
-6
0
6
% of
Z
TX_LOW_CM_DC
Z
RX_LOW_CM_DC
DC resistance of Rx terminations at half
the single ended swing (usually
0.25*V
Tx-diff-pp-pin
) bias point
38
52
Ω
ΔZ
RX_LOW_CM_DC
Defined as: ± (max(Z
RX_LOW_CM_DC
) -
min(Z
RX_LOW_CM_DC
))
/ Z
RX_LOW_CM_DC
expressed in %, over full range of Rx
single ended voltage
-6
0
6
% of
Z
RX_LOW_CM_DC
N
MIN-UI-Validation
# of UI over which the eye mask voltage
and timing spec needs to be validated
1,000,000
UI
Z
TX_HIGH_CM_DC
Single ended DC impedance to GND for
either D+ or D- of any data bit at Tx
10k
Ω
1