Intel E5645 AT80614003597AC User Manual
Product codes
AT80614003597AC
Electrical Specifications
50
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
When the single ended slew rate of the input Data or Strobe signals, within a byte group, are below 1.0
V/ns, the tSU and tHD specifications must be increased by a derating factor. The input single ended slew
rate is measured DC to AC levels; V
IL
_DC to V
IH
_AC for rising edges, and V
IH
_DC to V
IL
_AC for falling
edges. Use the worse case minimum slew rate measured between Data and Strobe, within a byte group, to
determine the required derating value. No derating is required for single ended slew rates equal to or
greater than 1.0 V/ns.
3.
Edge Placement Accuracy (EPA): The silicon contains digital logic that automatically adjusts the timing
relationship
between the DDR reference clocks and DDR signals. The BIOS initiates a training procedure
that will place a given
signal appropriately within the clock period. The difference in delay between the
signal and clock is accurate to
within ±EPA. This EPA includes jitter, skew, within die variation and several
other effects.
4.
Data to Strobe read setup and Data from Strobe read hold minimum requirements specified at the
processor pad are determined with the minimum Read DQS/DQS# delay.
T
SLR_D
DQ[63:0], DQS_P[17:0],
DQS_N[17:0], ECC[7:0]
Input Slew Rate
Input Slew Rate
4.0
1.0
V/ns
2
Clock Timings
T
CK
CLK Period
<2.50
1.875
ns
T
CH
CLK High Time
1.25
0.94
ns
T
CL
CLK Low Time
1.25
0.94
ns
T
SKEW
Skew Between Any System
Memory Differential Clock Pair
(CLK_P/CLK_N)
+155
ps
Command Signal Timings
T
CMD_CO
RAS#, CAS#, WE#, MA[15:0],
BA[2:0] Edge placement accuracy
+300
-300
ps
3,4,6
Control Signal Timings
T
CTRL_CS
CS#[7:0], CKE[3:0], ODT[3:0]
Edge placement accuracy
+300
-300
ps
3,6
Data and Strobe Signal Timings
T
DVA
+ T
DVB
DQ[63:0] Valid before and after
DQS[17:0] Rising or Falling Edge
0.67 * UI
UI
7
T
SU
+ T
HD
DQ Input Setup plus Hold Time to
DQS Rising or Falling Edge
0.25 * UI
ns
1,2,7
T
DQS_CO
DQS Edge Placement Accuracy to
CK Rising Edge BEFORE write
leveling
+300
-300
ns
3,6,7
T
DQS_CO
DQS Edge Placement Accuracy to
CK Rising Edge AFTER write
leveling
+206
-206
ns
3,6,7,8
T
WPRE
DQS/DQS# Write Preamble
Duration
1.781
ns
T
WPST
DQS/DQS# Write Postamble
Duration
1.031
0.844
ns
T
DQSS
CK Rising Edge Output Access
Time, Where a Write Command Is
Referenced, to the First DQS Rising
Edge
C
WL
x (T
CK
+ 4)
ns
5,6
Table 2-24. DDR3 Electrical Characteristics and AC Specifications at 1066 MT/s (Sheet 2
of 2)
Symbol
Parameter
Channel 0
Channel 1
Channel 2
Unit
Figure
Note
Max
Min