Genius 2793 User Manual
GND
47nF
Interlace (15KHz)
254
10uF
259
+
254
PN2222
257
100K
247
33K
256
200K
.047uF
318
355
1/4
LM339
13
11
10
+
356
3.92K
1.5-2VDC
59,D6
357
.05VDC
7V pp 60,C5
Vs,Hs
255
246
200K
1K
358
H
s
355
355
Horizontal
Sync
2
VC
1
Vertical
Sync
322
6.8K
6.8K
GND
V
s
270
Ω
270
Ω
1.8K
1.8K
270
Ω
331
325
326
330
1/4
LM339
1/4
LM339
327
22K
323
2
4
5
1
7
6
3
12
.14-.16V
+
+
321
328
0
Ω
GND
+12V
VC
318
0
Ω
257
1.8K
355
1/4
LM339
14
9
8
+
353
15.8K
354
360
364
366
7.15K
7.15K
2.1-2.4VDC
4.6Vpp 58,D6
Hs
15.8K
68.1K
Horizontal Sync
1K
246
+12V
Vertical Sync
FBP
PN2222
0
Ω
364
VERTICAL AND HORIZONTAL SYNC CIRCUIT DESCRIPTION.
Vertical Sync
Horizontal Sync
Sync Interface
2 Comparators
2 Comparators
Vertical Sync To Horizontal Cycle Synchronization
and Composite Sync Decoder
and Composite Sync Decoder
For Interlaced Vertical Sync.
{
Composite
Sync
To LA7851 pin 19
To LA7851 pin 1
Composite sync or separate vertical and horizontal sync
are buffered by two comparators in the sync interface
circuit. A vertical sync synchronization circuit is used to
insure a stable raster and functions as a sync separator.
are buffered by two comparators in the sync interface
circuit. A vertical sync synchronization circuit is used to
insure a stable raster and functions as a sync separator.
The synchronization circuit is bypassed, for interlaced
vertical sync, because this circuit rejects the half
horizontal line time variation used to generate the
interlaced vertical raster.
vertical sync, because this circuit rejects the half
horizontal line time variation used to generate the
interlaced vertical raster.
The sync interface comparators are biased to .15 volts,
by resistors
by resistors
323
&
327
, to permit receiving low level
sync signals such as RS170. For low level composite
sync, the vertical and horizontal lines are tied together
and jumper
sync, the vertical and horizontal lines are tied together
and jumper
328
is left off. For normal amplitude sync,
(greater than 2.3 volts) resistors
325
&
326
form an
attenuator to protect the sync interface comparators and
normalize the sync amplitude. This combination also
reduces noise sensitivity since the sync voltage amplitude
is low at the comparator input which slows the
comparator response and acts as a low pass filter.
normalize the sync amplitude. This combination also
reduces noise sensitivity since the sync voltage amplitude
is low at the comparator input which slows the
comparator response and acts as a low pass filter.
For the interlaced sync case, the pullup resistor
321
is
left off and the voltage divider resistors
246
and
257
act
as the pullup. Also the vertical sync synchronization
comparators are disabled by changing the input resistors
to bias the comparators in the high output state and
resistor
comparators are disabled by changing the input resistors
to bias the comparators in the high output state and
resistor
366
is left off. Capacitor
254
acts as a sync
separator for composite interlaced sync. Capacitor
259
and jumper
364
are used to couple the composite sync to
the LA7851 vertical sync input pin 19.
The vertical sync synchronization window comparator
generates a pulse, a little after the midpoint of each
horizontal cycle. This pulse is shorted to GND by
transistors
generates a pulse, a little after the midpoint of each
horizontal cycle. This pulse is shorted to GND by
transistors
255
except when vertical sync is active. The
two transistor circuit permits using either positive or
negative pulses for vertical sync.
negative pulses for vertical sync.
Capacitor
318
couples the vertical sync pulses to
transistors
254
&
255
. When no sync pulse is present,
transistor
255
is turned on by resistor
246
. For a
negative vertical sync pulse, transistor
255
is turned off
by the negative pulse applied to resistor
257
and the
window comparator pulse is allowed to be the vertical sync
pulse. For positive vertical sync pulse, transistor
pulse. For positive vertical sync pulse, transistor
254
is
turned on by resistor
247
&
256
, which shorts the base
of transistor
255
to GND also allowing the window
comparator pulse to act as the sync pulse.
A sawtooth waveform is produced on integrating
capacitor
capacitor
358
by applying the flyback pulse to resistors
360
&
357
. This sawtooth waveform is connected to two
comparators which are biased by resistors
353
,
356
,
354
, &
360
such that both comparator outputs are
high between 1.8 volts to 2.3 volts. This circuit would
produce a pulse on both the positive and negative slope
parts of the sawtooth waveform. Resistor
produce a pulse on both the positive and negative slope
parts of the sawtooth waveform. Resistor
357
eliminates
the output pulse on the negative slope by introducing part
of the flyback pulse to pin 8 which keeps the comparator
from going high at this time. Resistors
of the flyback pulse to pin 8 which keeps the comparator
from going high at this time. Resistors
364
&
366
act as
a pullup for the window comparator and apply a 6 volt bias
to the vertical sync input, LA7851 pin 19. At 6 volts, the
vertical sync input is inactive. It becomes active only
when the window comparator output and the ± sync
transistors are all high.
to the vertical sync input, LA7851 pin 19. At 6 volts, the
vertical sync input is inactive. It becomes active only
when the window comparator output and the ± sync
transistors are all high.
+
323
321
246
327
328
326
325
255
257
259
254
257
255
247
256
255
254
255
318
353
254
246
255
360
356
354
360
357
358
357
364
366
78
366
364