Intel N475 AU80610006240AA User Manual
Product codes
AU80610006240AA
Introduction
10
Datasheet
•
100-MHz reference clock
•
64-bit downstream address (only 36-bit addressable from the processor)
•
APIC messaging support. Will send Intel-defined “End of Interrupt” broadcast
message when initiated by the processor
message when initiated by the processor
•
Message Signaled Interrupt (MSI) messages supported
•
Power Management state change messages supported
•
SMI, SCI and SERR error indication
•
Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
DMA, floppy drive, and LPC bus masters
•
Hybrid AC-DC coupling solution between the processor and the chipset
•
Polarity inversion supported
1.2.3
Integrated Graphics Controller
•
The integrated graphics controller contains a refresh of the 3rd generation graphics
core
core
•
Intel
®
Dynamic Video Memory Technology 4.0
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Directx* 9 compliant Pixel Shader 2.0
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200-MHz render clock frequency
•
Two display ports: LVDS and RGB
— Integrated single LVDS channel support resolution up to 1280*800 or 1366*768
— Analog RGB display output up to resolution 1400x1050 @ 60Hz
•
Intel
®
Clear Video Technology
— MPEG2 Hardware Acceleration
— ProcAmp
1.3
Clocking
•
Differential Core clock of 166 MHz (BCLKP/BCLKN)
•
Differential Host clock of 166 MHz (HPL_CLKINP/HPL_CLKINN)
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The differential DMI clock of 100 MHz (EXP_CLKINP/EXP_CLKINN)
•
Display timings are generated from display PLLs that use a 96 MHz or 100 MHz
differential clock as reference.
differential clock as reference.
•
All of the above clocks are capable of tolerating Spread Spectrum clocking.
•
Memory clocks generated from internal Host PLLs
•
Host, Memory, DMI, Display PLLs and all associated internal clocks are disabled
until PWROK is asserted.
until PWROK is asserted.