Intel N475 AU80610006240AA User Manual
Product codes
AU80610006240AA
Datasheet
69
Thermal Specifications and Design Considerations
PROCHOT# will not be asserted when the processor is in the low power states like Stop
Grant and Deeper Sleep; hence, the thermal diode reading must be used as a
safeguard to maintain the processor junction temperature within maximum
specification. If the platform thermal solution is not able to maintain the processor
junction temperature within the maximum specification, the system must initiate an
orderly shutdown to prevent damage. If the processor enters one of the above power
states with PROCHOT# already asserted, PROCHOT# will remain asserted until the
processor exits the low power state and the processor junction temperature drops
below the thermal trip point.
Grant and Deeper Sleep; hence, the thermal diode reading must be used as a
safeguard to maintain the processor junction temperature within maximum
specification. If the platform thermal solution is not able to maintain the processor
junction temperature within the maximum specification, the system must initiate an
orderly shutdown to prevent damage. If the processor enters one of the above power
states with PROCHOT# already asserted, PROCHOT# will remain asserted until the
processor exits the low power state and the processor junction temperature drops
below the thermal trip point.
If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out
of specification. Regardless of enabling the automatic or on-demand modes, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached a temperature of approximately 125°C. At this point the
THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor
activity and does not generate any bus cycles. When THERMTRIP# is asserted, the
processor core voltage must be shut down within the time specified.
of specification. Regardless of enabling the automatic or on-demand modes, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached a temperature of approximately 125°C. At this point the
THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor
activity and does not generate any bus cycles. When THERMTRIP# is asserted, the
processor core voltage must be shut down within the time specified.
6.1.3
Digital Thermal Sensor
The processor also contains an on die Digital Thermal Sensor (DTS) that can be read
via an MSR (no I/O interface). The DTS is only valid while the processor is in the normal
operating state (the Normal package level low power state).
via an MSR (no I/O interface). The DTS is only valid while the processor is in the normal
operating state (the Normal package level low power state).
Unlike traditional thermal devices, the DTS will output a temperature relative to the
maximum supported operating temperature of the processor (T
maximum supported operating temperature of the processor (T
J_max
). It is the
responsibility of software to convert the relative temperature to an absolute
temperature. The temperature returned by the DTS will always be at or below T
temperature. The temperature returned by the DTS will always be at or below T
J_max
.
Catastrophic temperature conditions are detectable via an Out Of Spec status bit. This
bit is also part of the DTS MSR. When this bit is set, the processor is operating out of
specification and immediate shutdown of the system should occur. The processor
operation and code execution is not ensured once the activation of the Out of Spec
status bit is set.
bit is also part of the DTS MSR. When this bit is set, the processor is operating out of
specification and immediate shutdown of the system should occur. The processor
operation and code execution is not ensured once the activation of the Out of Spec
status bit is set.
The DTS-relative temperature readout corresponds to the Thermal Monitor 1(TM1) and
Thermal Monitor 2 (TM2) trigger points. When the DTS indicates maximum processor
core temperature has been reached, the TM1 or TM2 hardware thermal control
mechanism will activate. The DTS and TM1/TM2 temperature may not correspond to
the thermal diode reading since the thermal diode is located in a separate portion of
the die and thermal gradient between the DTS. Additionally, the thermal gradient from
DTS to thermal diode can vary substantially due to changes in processor power,
mechanical and thermal attach, and software application. The system designer is
required to use the DTS to ensure proper operation of the processor within its
temperature operating specifications.
Thermal Monitor 2 (TM2) trigger points. When the DTS indicates maximum processor
core temperature has been reached, the TM1 or TM2 hardware thermal control
mechanism will activate. The DTS and TM1/TM2 temperature may not correspond to
the thermal diode reading since the thermal diode is located in a separate portion of
the die and thermal gradient between the DTS. Additionally, the thermal gradient from
DTS to thermal diode can vary substantially due to changes in processor power,
mechanical and thermal attach, and software application. The system designer is
required to use the DTS to ensure proper operation of the processor within its
temperature operating specifications.
Changes to the temperature can be detected via two programmable thresholds located
in the processor MSRs. These thresholds have the capability of generating interrupts
via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software
Developer's Manuals for specific register and programming details.
in the processor MSRs. These thresholds have the capability of generating interrupts
via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software
Developer's Manuals for specific register and programming details.