Intel E5500 AT80571PG0722ML Data Sheet

30

Datasheet

NOTES:
1.

Unless otherwise noted, all specifications in this table apply to all processor core 
frequencies based on a 266 MHz BCLK[1:0].

2.

The period specified here is the average period. A given period may vary from this 
specification as governed by the period stability specification (T2). The Min period 
specification is based on -300 PPM deviation from a 3.75 ns period. The Max period 
specification is based on the summation of +300 PPM deviation from a 3.75 ns period and 
a +0.5% maximum variance due to spread spectrum clocking.

3.

In this context, period stability is defined as the worst case timing difference between 
successive crossover voltages. In other words, the largest absolute difference between 
adjacent clock periods must be less than the period stability.

4.

Slew rate is measured through the VSWING voltage range centered about differential zero. 
Measurement taken from differential waveform.

5.

Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is 
measured using a ±75 mV window centered on the average cross point where Clock rising 
meets Clock# falling. The median cross point is used to calculate the voltage thresholds 
the oscilloscope is to use for the edge rate calculations.

6.

Duty Cycle (High time/Period) must be between 40% and 60%

1.

Unless otherwise noted, all specifications in this table apply to all processor core frequencies

based on a 200 MHz BCLK[1:0].

BCLK[1:0] Frequency

198.980

—

200.020

MHz

-

2

2.

Duty Cycle (High time/Period) must be between 40 and 60%.

T1: BCLK[1:0] Period

4.99950

—

5.00050

ns

3

3. The period specified here is the average period. A given period may vary from this specification

as governed by the period stability specification (T2). Min period specification is based on 
-300 PPM deviation from a 5 ns period. Max period specification is based on the summation of
+300 PPM deviation from a 5 ns period and a +0.5% maximum variance due to spread spectrum

clocking.

T2: BCLK[1:0] Period Stability

—

—

150

ps

4

4.

In this context, period stability is defined as the worst case timing difference between successive

crossover voltages. In other words, the largest absolute difference between adjacent clock

periods must be less than the period stability.

T5: BCLK[1:0] Rise and Fall Slew Rate

2.5

—

8

V/nS

5

5.

Measurement taken from differential waveform.

T6: Slew Rate Matching

N/A

N/A

20

%

6

6.

Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured

using a ±75 mV window centered on the average cross point where Clock rising meets Clock#

falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to

use for the edge rate calculations. Slew rate matching is a single ended measurement.

BCLK[1:0] Frequency

265.307

-

266.693

MHz

-

6

T1: BCLK[1:0] Period

3.74963

-

3.76922

ns

2

T2: BCLK[1:0] Period Stability

-

-

150

ps

3

T5: BCLK[1:0] Rise and Fall Slew Rate

2.5

-

8

V/ns

4

Slew Rate Matching

N/A

N/A

20

%

-

5