Intel N455 AU80610006237AA User Manual

Intel

Product codes

AU80610006237AA

Specification Update

Intel Confidential

5

Figures

Platform Block Diagram........................................................................... 13

LVDS Signals and Swing Voltage .............................................................. 33

LVDS Clock and Data Relationship ............................................................ 33

Panel Power Sequencing.......................................................................... 34

and I

CC

Processor Loadline................................................................. 44

Idle Power Management Breakdown of the Processor Thread ........................ 56

Thread C-state....................................................................................... 57

Processor Core Low-power States ............................................................. 57

PM_EXTTS1#/DPSLPVR Implementation for Fast C4/C4E Exit ....................... 63

Package Mechanical Drawings .................................................................. 72

Package Pinmap (Top View, Upper-Left Quadrant) ...................................... 73

Package Pinmap (Top View, Upper-Right Quadrant) .................................... 74

Package Pinmap (Top View, Lower-Left Quadrant) ...................................... 75

Package Pinmap (Top View, Lower-Right Quadrant) .................................... 76

Tables

Signal Types .......................................................................................... 14

Signal Description Buffer Types ................................................................ 14

Processor Legacy Signals......................................................................... 15

System Memory Interface........................................................................ 18

Memory Reference and Compensation ....................................................... 19

Reset and Miscellaneous Signals ............................................................... 19

DMI - Processor to Chipset Serial Interface ................................................ 20

PLL Signals............................................................................................ 21

Analog Display Signals ............................................................................ 21

LVDS Signals ......................................................................................... 22

TAP Signals ........................................................................................... 22

Error and Thermal Protection ................................................................... 23

Processor Core Power Signals................................................................... 23

Power Signals ........................................................................................ 24

Ground ................................................................................................. 24

Supported SO-DIMM Module Configurations ............................................... 25

Analog Port Characteristics ...................................................................... 31

Panel Power Sequencing Timing Parameters............................................... 34

Voltage Identification Definition................................................................ 38

Processor Absolute Minimum and Maximum Ratings .................................... 41

Processor Core Active and Idle Mode DC Voltage and Current Specifications ... 43

Processor I/O Buffer Supply DC Voltage and Current Specifications ............... 45

Input Clocks (BCLK, HPL_CLKIN, REFCLKIN, EXP_CLKIN) Differential

Specification .......................................................................................... 46

DDR2 Signal Group DC Specifications........................................................ 46

GTL Signal Group DC Specifications .......................................................... 47

Legacy CMOS Signal Group DC Specification .............................................. 48

Open Drain Signal Group DC Specification.................................................. 49

PWROK and RSTIN# DC Specification........................................................ 49

CPUPWRGOOD DC Specification................................................................ 49

TAP Signal Group DC Specification ............................................................ 50