Intel N455 AU80610006237AA User Manual
Product codes
AU80610006237AA
Power Management
56
Datasheet
5.2.3.1
Clock Control and Low-Power States
The processor core supports low power states at the thread level and core/package
level. Thread states (TCx) loosely correspond to ACPI processor core power states (Cx).
A thread may independently enter TC1/AutoHALT, TC1/MWAIT, TC2, TC3 and TC4 lower
power states, but this does not always cause a power state transition. Only when both
threads request a low-power state (TCx) greater than the current processor core state
will a transition occur. The central power management logic ensures the entire
processor core enters the new common processor core power state. For processor core
power states higher than C1, this would be done by initiating a P_LVLx (P_LVL2,
P_LVL3, P_LVL4) I/O read to both threads. Package states are states that require
external intervention and typically map back to processor core power states. Package
states for processor core include Normal (C0, C1), and Stop Grant, Stop Grant Snoop
(C2), and Deeper Sleep (C4).
level. Thread states (TCx) loosely correspond to ACPI processor core power states (Cx).
A thread may independently enter TC1/AutoHALT, TC1/MWAIT, TC2, TC3 and TC4 lower
power states, but this does not always cause a power state transition. Only when both
threads request a low-power state (TCx) greater than the current processor core state
will a transition occur. The central power management logic ensures the entire
processor core enters the new common processor core power state. For processor core
power states higher than C1, this would be done by initiating a P_LVLx (P_LVL2,
P_LVL3, P_LVL4) I/O read to both threads. Package states are states that require
external intervention and typically map back to processor core power states. Package
states for processor core include Normal (C0, C1), and Stop Grant, Stop Grant Snoop
(C2), and Deeper Sleep (C4).
The processor core implements two software interfaces for requesting low power
states: MWAIT instruction extensions with sub-state hints and P_LVLx reads to the
ACPI P_BLK register block mapped in the processor core’s I/O address space. The
P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the
processor core and do not directly result in I/O reads on the processor core bus. The
monitor address does not need to be setup before using the P_LVLx I/O read interface.
The sub-state hints used for each P_LVLx read can be configured in a software
programmable MSR by BIOS. If a thread encounters a chipset break even while
STPCLK# is asserted, then it asserts the PBE# output signal. Assertion of PBE#
(multifunction of FERR#) when STPCLK# is asserted indicates to system logic that
individual threads should return to the C0 state and the processor core should return to
the Normal state.
states: MWAIT instruction extensions with sub-state hints and P_LVLx reads to the
ACPI P_BLK register block mapped in the processor core’s I/O address space. The
P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the
processor core and do not directly result in I/O reads on the processor core bus. The
monitor address does not need to be setup before using the P_LVLx I/O read interface.
The sub-state hints used for each P_LVLx read can be configured in a software
programmable MSR by BIOS. If a thread encounters a chipset break even while
STPCLK# is asserted, then it asserts the PBE# output signal. Assertion of PBE#
(multifunction of FERR#) when STPCLK# is asserted indicates to system logic that
individual threads should return to the C0 state and the processor core should return to
the Normal state.
Figure 5-6. Idle Power Management Breakdown of the Processor Thread
Processor Core/Package State
Thread 1 State
Thread 0 State