Apple II User Manual
0363 E0C0 78 SEI ;DISABLE INTERRUPT
0364 E0C1 A2 FF LDX #$FF ;INIT STACK PTR
0365 E0C3 9A TXS
0365 E0C3 9A TXS
0366 E0C4 8E 24 A4 STX SAVS ;ALSO INIT SAVED STACK PTR
0367 E0C7 ;INITIALIZE 6522
0367 E0C7 ;INITIALIZE 6522
0368 E0C7 A2 0E LDX #14
0369 E0C9 BD 43 E7 RS1 LDA INTAB1,X ;PB1-PB0,PA7-PA0 FOR PRNTR
0369 E0C9 BD 43 E7 RS1 LDA INTAB1,X ;PB1-PB0,PA7-PA0 FOR PRNTR
0370 E0CC 9D 00 A8 STA DRB,X ;PB2=TTO,PB6=TTI
0371 E0CF CA DEX ;PB4-PB5=TAPE CONTROL,PB7=DATA
0371 E0CF CA DEX ;PB4-PB5=TAPE CONTROL,PB7=DATA
0372 E0D0 10 F7 BPL RS1 ;PB3 =SWITCH KB/TTY
0373 E0D2 ;INITIALIZE 6532
0373 E0D2 ;INITIALIZE 6532
0374 E0D2 A2 03 LDX #3 ;PORTS USED FOR KB
0375 E0D4 BD 52 E7 RS2 LDA INTAB2,X ;PA0-PA7 AS OUTPUT
0375 E0D4 BD 52 E7 RS2 LDA INTAB2,X ;PA0-PA7 AS OUTPUT
0376 E0D7 9D 80 A4 STA DRA2,X ;PB0-PB7 AS INPUT
0377 E0DA CA DEX
0377 E0DA CA DEX
0378 E0DB 10 F7 BPL RS2
0379 E0DD ;INITIALIZE MONITOR RAM (6532)
0379 E0DD ;INITIALIZE MONITOR RAM (6532)
0380 E0DD AD 56 E7 LDA INTAB3 ;CHECK IF NMIV2 HAS BEEN CHANGED
0381 E0E0 CD 02 A4 CMP NMIV2 ;IF IT HAS THEN ASSUME A COLD
0381 E0E0 CD 02 A4 CMP NMIV2 ;IF IT HAS THEN ASSUME A COLD
0382 E0E3 D0 0C BNE RS3A ;START AND INITIALIZE EVERYTHING
0383 E0E5 AD 57 E7 LDA INTAB3+1
0383 E0E5 AD 57 E7 LDA INTAB3+1
0384 E0E8 CD 03 A4 CMP NMIV2+1
0385 E0EB D0 04 BNE RS3A
0385 E0EB D0 04 BNE RS3A
0386 E0ED A2 10 LDX #16 ;THEY ARE EQUAL ,IT'S A WARM RESET
0387 E0EF D0 02 BNE RS3
0387 E0EF D0 02 BNE RS3
0388 E0F1 A2 00 RS3A LDX #0 ;INIT EVERYTHING (POWER UP)
0389 E0F3 BD 56 E7 RS3 LDA INTAB3,X
0389 E0F3 BD 56 E7 RS3 LDA INTAB3,X
0390 E0F6 9D 02 A4 STA NMIV2,X
0391 E0F9 E8 INX
0391 E0F9 E8 INX
0392 E0FA E0 15 CPX #21
0393 E0FC 90 F5 BCC RS3
0393 E0FC 90 F5 BCC RS3
0394 E0FE ;INITIALIZE DISPLAY (6520)
0395 E0FE A9 00 LDA #0 ;SET CONTR REG FOR DATA DIR REG
0395 E0FE A9 00 LDA #0 ;SET CONTR REG FOR DATA DIR REG
0396 E100 A2 01 LDX #1
0397 E102 20 13 E1 JSR SETREG
0397 E102 20 13 E1 JSR SETREG
0398 E105 A9 FF LDA #$FF ;SET DATA DIR REG FOR OUTPUT
0399 E107 CA DEX
0399 E107 CA DEX
0400 E108 20 13 E1 JSR SETREG
0401 E10B A9 04 LDA #$04 ;SET CONTR REG FOR PORTS
0401 E10B A9 04 LDA #$04 ;SET CONTR REG FOR PORTS
0402 E10D E8 INX
0403 E10E 20 13 E1 JSR SETREG
0403 E10E 20 13 E1 JSR SETREG
0404 E111 D0 07 BNE RS3B
0405 E113 9D 00 AC SETREG STA RA,X
0405 E113 9D 00 AC SETREG STA RA,X
0406 E116 9D 02 AC STA RB,X
0407 E119 60 RTS
0407 E119 60 RTS
0408 E11A 58 RS3B CLI ;CLEAR INTERRUPT
0409 E11B
0409 E11B
0410 E11B ;KB/TTY SWITCH TEST AND BIT RATE MEASUREMENT
0411 E11B A9 08 LDA #$08 ;PB3=SWITCH KB/TTY
0411 E11B A9 08 LDA #$08 ;PB3=SWITCH KB/TTY
0412 E11D 2C 00 A8 RS4 BIT DRB ;A^M ,PB6-> V (OVERFLOW FLG)
0413 E120 D0 22 BNE RS7 ;BRANCH ON KB
0413 E120 D0 22 BNE RS7 ;BRANCH ON KB
0414 E122 70 F9 BVS RS4 ;START BIT=PB6=0?
0415 E124 A9 FF LDA #$FF ;YES ,INITIALIZE TIMER T2
0415 E124 A9 FF LDA #$FF ;YES ,INITIALIZE TIMER T2
0416 E126 8D 09 A8 STA T2H
0417 E129 2C 00 A8 RS5 BIT DRB ;END OF START BIT ?
0417 E129 2C 00 A8 RS5 BIT DRB ;END OF START BIT ?
0418 E12C 50 FB BVC RS5 ;NO ,WAIT UNTIL PB6 BACK TO 1
0419 E12E AD 09 A8 LDA T2H ;STORE TIMING
0419 E12E AD 09 A8 LDA T2H ;STORE TIMING
0420 E131 49 FF EOR #$FF ;COMPLEMENT
0421 E133 8D 17 A4 STA CNTH30
0421 E133 8D 17 A4 STA CNTH30
0422 E136 AD 08 A8 LDA T2L
0423 E139 49 FF EOR #$FF
0423 E139 49 FF EOR #$FF
0424 E13B 20 7C FE JSR PATCH1 ;ADJUST IT