Apple II User Manual
2709 F24A ;OUTPUT ACC TO TAPE
2710 F24A 8E 2D A4 OUTTAP STX CPIY+3 ;SAVE X
2711 F24D A0 07 LDY #$07 ;FOR THE 8 BITS
2711 F24D A0 07 LDY #$07 ;FOR THE 8 BITS
2712 F24F 8C 27 A4 STY STIY
2713 F252 AE 08 A4 LDX TSPEED
2713 F252 AE 08 A4 LDX TSPEED
2714 F255 30 39 BMI OUTTA1 ;IF ONE IS SUPER HIPER
2715 F257 48 PHA
2715 F257 48 PHA
2716 F258 A0 02 TRY LDY #2 ;SEND 3 UNITS
2717 F25A 8C 28 A4 STY STIY+1 ;STARTING AT 3700 HZ
2717 F25A 8C 28 A4 STY STIY+1 ;STARTING AT 3700 HZ
2718 F25D BE 0A A4 ZON LDX NPUL,Y ;#OF HALF CYCLES
2719 F260 48 PHA
2719 F260 48 PHA
2720 F261 B9 0B A4 ZON1 LDA TIMG,Y ;SET UP LACTH FOR NEXT
2721 F264 8D 06 A8 STA T1LL ;PULSE (80 OR CA) (FREC)
2721 F264 8D 06 A8 STA T1LL ;PULSE (80 OR CA) (FREC)
2722 F267 A9 00 LDA #0
2723 F269 8D 07 A8 STA T1LH
2723 F269 8D 07 A8 STA T1LH
2724 F26C 2C 0D A8 ZON2 BIT IFR ;WAIT FOR PREVIOUS
2725 F26F 50 FB BVC ZON2 ;CYCLE (T1 INT FLG)
2725 F26F 50 FB BVC ZON2 ;CYCLE (T1 INT FLG)
2726 F271 AD 04 A8 LDA T1L ;CLR INTERR FLG
2727 F274 CA DEX
2727 F274 CA DEX
2728 F275 D0 EA BNE ZON1 ;SEND ALL CYCLES
2729 F277 68 PLA
2729 F277 68 PLA
2730 F278 CE 28 A4 DEC STIY+1
2731 F27B F0 05 BEQ SETZ ;BRCH IF LAST ONE
2731 F27B F0 05 BEQ SETZ ;BRCH IF LAST ONE
2732 F27D 30 07 BMI ROUT ;BRCH IF NO MORE
2733 F27F 4A LSR A ;TAKE NEXT BIT
2733 F27F 4A LSR A ;TAKE NEXT BIT
2734 F280 90 DB BCC ZON ;...IF IT'S A ONE...
2735 F282 A0 00 SETZ LDY #0 ;SWITCH TO 2400 HZ
2735 F282 A0 00 SETZ LDY #0 ;SWITCH TO 2400 HZ
2736 F284 F0 D7 BEQ ZON ;UNCONDITIONAL BRCH
2737 F286 CE 27 A4 ROUT DEC STIY ;ONE LESS BIT
2737 F286 CE 27 A4 ROUT DEC STIY ;ONE LESS BIT
2738 F289 10 CD BPL TRY ;ANY MORE? GO BACK
2739 F28B 68 ROUT1 PLA ;RECOVER CHR
2739 F28B 68 ROUT1 PLA ;RECOVER CHR
2740 F28C AE 2D A4 LDX CPIY+3 ;RESTORE X
2741 F28F 60 RTS
2741 F28F 60 RTS
2742 F290
2743 F290 ;OUTPUT HALF PULSE FOR 0 (1200 HZ) &
2743 F290 ;OUTPUT HALF PULSE FOR 0 (1200 HZ) &
2744 F290 ;TWO HALF PULSES FOR 1 (2400 HZ) (00 TSPEED)
2745 F290 48 OUTTA1 PHA
2745 F290 48 OUTTA1 PHA
2746 F291 8D 28 A4 STA STIY+1 ;STORE ACC
2747 F294 A2 02 OUTTA2 LDX #2 ;# OF HALF PULSES
2747 F294 A2 02 OUTTA2 LDX #2 ;# OF HALF PULSES
2748 F296 A9 D0 LDA #$D0 ;1/2 PULSE OF 2400
2749 F298 8D 06 A8 STA T1LL
2749 F298 8D 06 A8 STA T1LL
2750 F29B A9 00 LDA #00
2751 F29D 8D 07 A8 STA T1LH
2751 F29D 8D 07 A8 STA T1LH
2752 F2A0 20 BC FF JSR PATC25 ;WAIT TILL COMPLETED
2753 F2A3 4E 28 A4 LSR STIY+1 ;GET BITS FROM CHR
2753 F2A3 4E 28 A4 LSR STIY+1 ;GET BITS FROM CHR
2754 F2A6 B0 0A BCS OUTTA3
2755 F2A8 A9 A0 LDA #$A0 ;BIT=0 ,OUTPUT 1200 HZ
2755 F2A8 A9 A0 LDA #$A0 ;BIT=0 ,OUTPUT 1200 HZ
2756 F2AA 8D 06 A8 STA T1LL
2757 F2AD A9 01 LDA #$01
2757 F2AD A9 01 LDA #$01
2758 F2AF 8D 07 A8 STA T1LH
2759 F2B2 20 BC FF OUTTA3 JSR PATC25
2759 F2B2 20 BC FF OUTTA3 JSR PATC25
2760 F2B5 CA DEX
2761 F2B6 10 FA BPL OUTTA3 ;OUTPUT 3 HALF PULSES
2761 F2B6 10 FA BPL OUTTA3 ;OUTPUT 3 HALF PULSES
2762 F2B8 88 DEY
2763 F2B9 10 D9 BPL OUTTA2 ;ALL BITS ?
2763 F2B9 10 D9 BPL OUTTA2 ;ALL BITS ?
2764 F2BB 4C 8B F2 JMP ROUT1 ;RESTORE REGS
2765 F2BE EA NOP
2765 F2BE EA NOP
2766 F2BF EA NOP
2767 F2C0
2767 F2C0
2768 F2C0 ;SET SPEED FROM NORMAL TO 3 TIMES NORMAL
2769 F2C0 AD 08 A4 SETSPD LDA TSPEED ;SPEED FLG
2769 F2C0 AD 08 A4 SETSPD LDA TSPEED ;SPEED FLG
2770 F2C3 6A ROR A ;NORMAL OR 3* NORM