Apple II User Manual
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| TOPIC -- Apple II -- Red Book Sweet-16 listing
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1 ***********************
2 * *
3 * APPLE-II PSEUDO *
3 * APPLE-II PSEUDO *
4 * MACHINE INTERPRETER *
5 * *
5 * *
6 * COPYRIGHT 1977 *
7 * APPLE COMPUTER INC *
7 * APPLE COMPUTER INC *
8 * *
9 * ALL RIGHTS RESERVED *
9 * ALL RIGHTS RESERVED *
10 * S. WOZNIAK *
11 * *
11 * *
12 ***********************
13 ; TITLE "SWEET16 INTERPRETER"
13 ; TITLE "SWEET16 INTERPRETER"
14 R0L EQU $0
15 R0H EQU $1
15 R0H EQU $1
16 R14H EQU $1D
17 R15L EQU $1E
17 R15L EQU $1E
18 R15H EQU $1F
19 SW16PAG EQU $F7
19 SW16PAG EQU $F7
20 SAVE EQU $FF4A
21 RESTORE EQU $FF3F
21 RESTORE EQU $FF3F
22 ORG $F689
F689: 20 4A FF 23 SW16 JSR SAVE ;PRESERVE 6502 REG CONTENTS
F689: 20 4A FF 23 SW16 JSR SAVE ;PRESERVE 6502 REG CONTENTS
F68C: 68 24 PLA
F68D: 85 1E 25 STA R15L ;INIT SWEET16 PC
F68D: 85 1E 25 STA R15L ;INIT SWEET16 PC
F68F: 68 26 PLA ;FROM RETURN
F690: 85 1F 27 STA R15H ; ADDRESS
F690: 85 1F 27 STA R15H ; ADDRESS
F692: 20 98 F6 28 SW16B JSR SW16C ;INTERPRET AND EXECUTE
F695: 4C 92 F6 29 JMP SW16B ;ONE SWEET16 INSTR.
F695: 4C 92 F6 29 JMP SW16B ;ONE SWEET16 INSTR.
F698: E6 1E 30 SW16C INC R15L
F69A: D0 02 31 BNE SW16D ;INCR SWEET16 PC FOR FETCH
F69A: D0 02 31 BNE SW16D ;INCR SWEET16 PC FOR FETCH
F69C: E6 1F 32 INC R15H
F69E: A9 F7 33 SW16D LDA #SW16PAG
F69E: A9 F7 33 SW16D LDA #SW16PAG
F6A0: 48 34 PHA ;PUSH ON STACK FOR RTS
F6A1: A0 00 35 LDY #$0
F6A1: A0 00 35 LDY #$0
F6A3: B1 1E 36 LDA (R15L),Y ;FETCH INSTR
F6A5: 29 0F 37 AND #$F ;MASK REG SPECIFICATION
F6A5: 29 0F 37 AND #$F ;MASK REG SPECIFICATION
F6A7: 0A 38 ASL ;DOUBLE FOR TWO BYTE REGISTERS
F6A8: AA 39 TAX ;TO X REG FOR INDEXING
F6A8: AA 39 TAX ;TO X REG FOR INDEXING
F6A9: 4A 40 LSR
F6AA: 51 1E 41 EOR (R15L),Y ;NOW HAVE OPCODE
F6AA: 51 1E 41 EOR (R15L),Y ;NOW HAVE OPCODE
F6AC: F0 0B 42 BEQ TOBR ;IF ZERO THEN NON-REG OP
F6AE: 86 1D 43 STX R14H ;INDICATE'PRIOR RESULT REG'
F6AE: 86 1D 43 STX R14H ;INDICATE'PRIOR RESULT REG'
F6B0: 4A 44 LSR
F6B1: 4A 45 LSR ;OPCODE*2 TO LSB'S
F6B1: 4A 45 LSR ;OPCODE*2 TO LSB'S
F6B2: 4A 46 LSR
F6B3: A8 47 TAY ;TO Y REG FOR INDEXING
F6B3: A8 47 TAY ;TO Y REG FOR INDEXING
F6B4: B9 E1 F6 48 LDA OPTBL-2,Y ;LOW ORDER ADR BYTE
F6B7: 48 49 PHA ;ONTO STACK
F6B7: 48 49 PHA ;ONTO STACK
F6B8: 60 50 RTS ;GOTO REG-OP ROUTINE
F6B9: E6 1E 51 TOBR INC R15L
F6B9: E6 1E 51 TOBR INC R15L
F6BB: D0 02 52 BNE TOBR2 ;INCR PC
F6BD: E6 1F 53 INC R15H
F6BD: E6 1F 53 INC R15H
F6BF: BD E4 F6 54 TOBR2 LDA BRTBL,X ;LOW ORDER ADR BYTE
F6C2: 48 55 PHA ;ONTO STACK FOR NON-REG OP
F6C2: 48 55 PHA ;ONTO STACK FOR NON-REG OP
F6C3: A5 1D 56 LDA R14H ;'PRIOR RESULT REG' INDEX