Apple II User Manual

30A  41         MLOOP   LD    @R1      ;R1 holds source

30B  52                 ST    @R2      ;R2 holds dest. addr.

30C  F3                 DCR   R3       ;Decr. length

30D  07 FB              BNZ   MLOOP    ;Loop until done

30F  00                 RTN            ;Return to 6502 mode.

310  C9 C5      NOMOVE  CMP   #"E"     ;"E" char?

312  D0 13              BEQ   EXIT     ;Yes, exit

314  C8                 INY            ;No, cont.

NOTE:  Registers A, X, Y, P, and S are not disturbed by SWEET 16.

Instruction Descriptions:

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The SWEET 16 opcode listing is short and uncomplicated. Excepting

relative branch displacements, hand assembly is trivial. All

register opcodes are formed by combining two Hex digits, one for the

opcode and one to specify a register. For example, opcodes 15 and

45 both specify register R5 while codes 23, 27, and 29 are all ST

ops. Most register ops are assigned in complementary pairs to

facilitate remembering them. Therefore, LD ans ST are opcodes 2N

and 3N respectively, while LD @ and ST @ are codes 4N and 5N.

Opcodes 0 to C (Hex) are assigned to the thirteen non-register ops.

Except for RTN (opcode 0), BK (0A), and RS (0B), the non register

ops are 6502 style branches. The second byte of a branch instruction

contains a +/-127 byte displacement value (in two's complement form)

relative to the address of the instruction immediately following

the branch.

If a specified branch condition is met by the prior register op

result, the displacement is added to the PC effecting a branch.

Except for the BR (Branch always) and BS (Branch to a Subroutine),

the branch opcodes are assigned in complementary pairs, rendering

them easily remembered for hand coding. For example, Branch if Plus

and Branch if Minus are opcodes 4 and 5 while Branch if Zero and

Branch if NonZero are opcodes 6 and 7.

SWEET 16 Opcode Summary:

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Register OPS-

     1n        SET       Rn     Constant  (Set)

     2n        LD        Rn     (Load)

     3n        ST        Rn     (Store)

     4n        LD        @Rn    (Load Indirect)

     5n        ST        @Rn    (Store Indirect)

     6n        LDD       @Rn    (Load Double Indirect)

     7n        STD       @Rn    (Store Double Indirect)

     8n        POP       @Rn    (Pop Indirect)

     9n        STP       @Rn    (Store POP Indirect)

     An        ADD       Rn     (Add)

     Bn        SUB       Rn     (Sub)

     Cn        POPD      @Rn    (Pop Double Indirect)

     Dn        CPR       Rn     (Compare)