Apple II User Manual

truncated to contain the 24 most significant mantissa bits (including

sign).  The absolute value of the multiplier mantissa (M2) is left in FP2.

E, SIGN, and SCR are altered.  The A- and X-REGs are altered and the Y-REG

contains $FF upon exit.

Cautions: An exit to location $3F5 is taken if the product is less than

-2^128 or greater than +2^128-1.

Notes: FMUL will run faster if the absolute value of the multiplier

mantissa contains fewer '1's than the absolute value of the multiplicand

mantissa.

Example: Prior to calling FMUL, FP1 contains +12 and FP2 contains -5.

      _____    _____    _____    _____

     |     |  |     |  |     |  |     |

FP1: | $83 |  | $60 |  |  0  |  |  0  |   (+12)

     |_____|  |_____|  |_____|  |_____|

       X1       M1

      _____    _____    _____    _____

     |     |  |     |  |     |  |     |

FP2: | $82 |  | $B0 |  |  0  |  |  0  |   (- 5)

     |_____|  |_____|  |_____|  |_____|

       X2       M2

After calling FMUL, FP1 contains -60 and FP2 contains +5.

      _____    _____    _____    _____

     |     |  |     |  |     |  |     |

FP1: | $85 |  | $88 |  |  0  |  |  0  |   (-60)

     |_____|  |_____|  |_____|  |_____|

       X1       M1

      _____    _____    _____    _____

     |     |  |     |  |     |  |     |

FP2: | $82 |  | $50 |  |  0  |  |  0  |   (+ 5)

     |_____|  |_____|  |_____|  |_____|

       X2       M2

FDIV subroutine (addr $F4B2)

Purpose: To perform division of floating point numbers.

Entry: The normalized dividend is in FP2 and the normalized divisor is in

FP1.

Exit: The signed normalized floating point quotient is left in FP1.  The

mantissa (M1) is truncated to 24 bits.  The 3-bit M1 extension (E) contains

the absolute value of the divisor mantissa.  MD2, SIGN, and SCR are