Motorola CPX8000 User Manual
1-16
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System Architecture
1
Hot Swap Control Status Register (CSR)
The CPX8216 supports hot swap CompactPCI cards with the standard
control status register defined by the PICMG Hot Swap Specification. The
register is visible in PCI configuration space and provides hot swap control
and status bits: INS and EXT. The INS signal is set when ENUM# is
asserted by a board being inserted into the system. The EXT signal is
asserted when ENUM# is asserted by an operator triggering the
microswitch in the board handles. The host also uses these bits to
acknowledge and de-assert ENUM#.
control status register defined by the PICMG Hot Swap Specification. The
register is visible in PCI configuration space and provides hot swap control
and status bits: INS and EXT. The INS signal is set when ENUM# is
asserted by a board being inserted into the system. The EXT signal is
asserted when ENUM# is asserted by an operator triggering the
microswitch in the board handles. The host also uses these bits to
acknowledge and de-assert ENUM#.
The Hot Swap Process
PICMG divided the complete hot swap process into physical, hardware
and software connection processes. These processes are formally broken
down further into a group of transitional states, which are illustrated in the
following figure.
and software connection processes. These processes are formally broken
down further into a group of transitional states, which are illustrated in the
following figure.
When inserting a board, it goes through all states from P0 to S3.
Conversely, a board transitions from S3 to P0 before being extracted.
During normal operation, no states are skipped. Extracting a board in a
software connection state other than S0 is likely to disrupt software enough
to crash the system, but the CompactPCI bus, from a purely electrical point
of view, will not be disrupted enough to cause logic levels to be violated.
Conversely, a board transitions from S3 to P0 before being extracted.
During normal operation, no states are skipped. Extracting a board in a
software connection state other than S0 is likely to disrupt software enough
to crash the system, but the CompactPCI bus, from a purely electrical point
of view, will not be disrupted enough to cause logic levels to be violated.
Certain states are overlapping. For example, when the board is fully seated
(completed P1), but has not yet started the hardware connection process
(completed P1), but has not yet started the hardware connection process
P0
P1
H 0
H 1
S1
H 2
S0
S2
S3
PH Y SIC AL
C O N N EC T IO N
S T AT ES
H AR D W A R E
C O N N E C T IO N ST AT E S
SO F T W A R E
C O N N E C T IO N
S T AT ES
H 1F
S2 Q
S3 Q