Samsung 100737108-A User Manual
Spinpoint M8-DVR OEM Product Manual REV 1.0
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Additional functionality is provided in the Buffer Control block through the following features:
Increased automation to support minimal latency read operations with minimal latency.
Capability to support the execution of multiple consecutive Auto-Write commands without
Increased automation to support minimal latency read operations with minimal latency.
Capability to support the execution of multiple consecutive Auto-Write commands without
loss of data due to overwriting of data.
Auto write pointer.
A disk sector counter that can monitor the transfers between the disk and buffer.
Read/Write cache support.
A disk sector counter that can monitor the transfers between the disk and buffer.
Read/Write cache support.
5.2.2.3 The Disk Control Block
The Spinpoint M8 Disk Control block manages the flow of data between the disk and the buffer. It is capable of
performing completely automated track read and write operations at a maximum data rate of 800 Mb/s in byte wide
NRZ mode. Many flexible features and elements of automation have been incorporated to complement the
automation contributed by the Host and Buffer blocks.
The Disk Control block consists of the programmable sequencer (Disk Sequencer), CDR/data split logic, disk FIFO,
fault tolerant sync detect logic, and other support logic.
The programmable sequencer contains a 31-by-4 byte programmable SRAM and associated control logic, which is
programmed by the user to automatically control all single track format, read, and write operations. From within the
sequencer micro program, the Disk Control block can automatically deal with such real time functions as defect
skipping, servo burst data splitting, branching on critical buffer status and data compare operations. Once the Disk
Sequencer is started, it executes each word in logical order. At the completion of the current instruction word, it
either continues to the next instruction, continues to execute some other instruction based upon an internal or
external condition having been met, or it stops.
During instruction execution or while stopped, registers can be accessed by the DSP to obtain status
information reflecting the Disk Sequencer operations taking place.
performing completely automated track read and write operations at a maximum data rate of 800 Mb/s in byte wide
NRZ mode. Many flexible features and elements of automation have been incorporated to complement the
automation contributed by the Host and Buffer blocks.
The Disk Control block consists of the programmable sequencer (Disk Sequencer), CDR/data split logic, disk FIFO,
fault tolerant sync detect logic, and other support logic.
The programmable sequencer contains a 31-by-4 byte programmable SRAM and associated control logic, which is
programmed by the user to automatically control all single track format, read, and write operations. From within the
sequencer micro program, the Disk Control block can automatically deal with such real time functions as defect
skipping, servo burst data splitting, branching on critical buffer status and data compare operations. Once the Disk
Sequencer is started, it executes each word in logical order. At the completion of the current instruction word, it
either continues to the next instruction, continues to execute some other instruction based upon an internal or
external condition having been met, or it stops.
During instruction execution or while stopped, registers can be accessed by the DSP to obtain status
information reflecting the Disk Sequencer operations taking place.
5.2.2.4 The Disk LDPC Control Block
The Disk Control Block supports a programmable LDPC code. Error detection and correction is handled in
the Disk Control block. Automatic on-the-fly hardware correction will take place. Correction is guaranteed to
complete before the parity bits of the sector following the sector where the error occurred utilizing standard
ATA size sectors.
the Disk Control block. Automatic on-the-fly hardware correction will take place. Correction is guaranteed to
complete before the parity bits of the sector following the sector where the error occurred utilizing standard
ATA size sectors.
5.2.2.5 Frequency Synthesizer
The frequency synthesizer is a clock frequency generation circuit used to generate a DSP clock, AT disk
controller and servo clock from the External Reference clock input.
controller and servo clock from the External Reference clock input.