Maxtor 10K III User Manual
Feature Descriptions
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Maxtor Atlas 10K III
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A 10,000 rpm rotation speed yields an average latency of 3 ms.
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Embedded servo information is written in a spoke configuration on every track, on
every disk surface. The spokes (or headers) consist of quadrature analog patterns and
digital address data. The digital portions of the spoke data are read and used to locate
the desired track, spoke, and head number. The quadrature analog signal portion is
detected and used by a servo feedback control loop to precisely position the head on
the track center.
every disk surface. The spokes (or headers) consist of quadrature analog patterns and
digital address data. The digital portions of the spoke data are read and used to locate
the desired track, spoke, and head number. The quadrature analog signal portion is
detected and used by a servo feedback control loop to precisely position the head on
the track center.
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The disk drives use a combination of parity checking, error detection coding (EDC),
error correction coding (ECC), and checkpointing to protect stored data from media
errors, transfer or addressing errors, or errors introduced during block reallocation.
error correction coding (ECC), and checkpointing to protect stored data from media
errors, transfer or addressing errors, or errors introduced during block reallocation.
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To ensure that data read is the same as data written, the drive computes and appends
an Error Correction Code (ECC) to each block of data stored. The drive uses a 352-
bit Reed Solomon code with a 4:1 interleave, which can correct up to 20 bytes in
each block.
an Error Correction Code (ECC) to each block of data stored. The drive uses a 352-
bit Reed Solomon code with a 4:1 interleave, which can correct up to 20 bytes in
each block.
The drive can also correct up to 2 bytes per interleave (up to 8 per block) in hardware
(“on-the-fly”), with no loss in throughput.
(“on-the-fly”), with no loss in throughput.
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An end-to-end error detection code (EDC) protects data from any errors introduced
by internal buses, the disk controller chip, the data cache, or the SCSI interface.
by internal buses, the disk controller chip, the data cache, or the SCSI interface.
An EDC is calculated and added to each data block as the data arrives from the SCSI
bus (after SCSI bus parity is checked). The EDC is stored with the data and protected
by the block ECC for added security. On reading or writing, the EDC is checked as
the data is transferred between buffer RAM and the media or the SCSI bus.
bus (after SCSI bus parity is checked). The EDC is stored with the data and protected
by the block ECC for added security. On reading or writing, the EDC is checked as
the data is transferred between buffer RAM and the media or the SCSI bus.
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Each data block on the media is identified and located by a servo spoke address. The
spoke address consists of a two-byte word. Each spoke has multiple copies of the least
significant bytes of the address. The disk hardware requires that a majority of the
copies agree and that the result agrees with the expected head, track, and spoke
number, before it will read or write the data.
spoke address consists of a two-byte word. Each spoke has multiple copies of the least
significant bytes of the address. The disk hardware requires that a majority of the
copies agree and that the result agrees with the expected head, track, and spoke
number, before it will read or write the data.
To further protect against addressing errors, the logical address (LBA) of the data is
added to the EDC of each block. If data is written to the wrong block and
subsequently read, or read from the wrong block, the error will be flagged.
added to the EDC of each block. If data is written to the wrong block and
subsequently read, or read from the wrong block, the error will be flagged.
The hardware does not allow a blind read of a data block; the firmware must request
specific data blocks. Even if the head selection hardware malfunctions, it is not possible
for the drive to return data from the wrong head.
specific data blocks. Even if the head selection hardware malfunctions, it is not possible
for the drive to return data from the wrong head.