Hitachi HUS154530VLF400 User Manual

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Hitachi Ultrastar 15K450 (FC-AL) Hard Disk Drive Specification
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• IGRA (Ignore Reassigned LBA) bit works in conjunction with the RC bit (Mode Page 01h, byte 2, bit 4).  The main pur-
pose of this bit is to avoid undesirable read processing time delays due to reassigned LBA processing for continuous 
data availability requirements such as Audio Visual applications.  If IGRA is set to one and RC is set to one, out-of-
line reassigned LBAs will not be processed.  If IGRA is set to one and RC is set to zero, or if IGRA is set to zero, 
reassigned LBAs will be processed normally.
• AVERP (AV ERP Mode) bit is set to one in order to specify maximum retry counts during Read DRP. When AVERP bit 
is set to one, the maximum retry counts for read operations is specified by Read Retry Count (Mode Page 1 Byte 3). 
AVERP bit is set to zero to specify that the drive shall process read DRP up to the default maximum retry count when 
Read Retry Count is set to a non-zero value.
• OCT  (Overall Command Timer) controls the maximum command execution time, from receipt by the drive until status 
is returned.  If the command is unable to complete in the specified amount of time, it will be aborted with Check Con-
dition status, Aborted Command sense key.  The Overall Command Timer does not alter the behavior of the Com-
mand Aging Limit or Recovery Time Limit.  Each unit of this timer is 50 milliseconds.  Setting the value to zero 
disabled the feature.
• Temperature Threshold specifies the threshold value in degrees Celsius for the thermal sensor warning message. A 
value of 0 selects the default value (85 degrees Celsius).
• Command Aging Limit This value controls the maximum time a command should wait in the command queue when the 
CAEN bit is set. Each unit of this timer is 50 ms.
•  Read Reporting Threshold specifies the error reporting threshold for recovered data errors during read operations 
when PER=1.
•  Write Reporting Threshold specifies the error reporting threshold for recovered data errors during write operations 
when PER=1.
• DRRT (Disable Restore Reassign Target) bit disables the reading and restoration of the target LBA during a Reassign 
Blocks command. If the DRRT bit is zero, the reassign command attempts to restore the target LBA's data. If the data 
cannot be restored, the target LBA is reassigned and written with a data pattern of all 00s. If the DRRT bit is one, no 
attempt is made to restore the target LBA.
• FFMT (Fast Format Enable) bit allows the formatting of the drive without any writes to the customer media. All format 
operations are allowed including changing block sizes and manipulating defects. The drive will operate normally 
after a fast format with the following caveat: since no data is written to any customer data blocks as a result of a Fast 
Format operation, there is a possibility that a read attempt to any particular block (without having previously written 
to that block) will result in an unrecoverable data error. This will most likely happen if the block size is changed as 
every LBA will contain data of an incorrect length and apparently an incorrect starting point. It is also possible to 
generate an uncorrectable data error without changing block sizes if the defect list is shortened and previously bad 
blocks become visible in the customer address space. Of course ALL DATA ON THE DRIVE WILL BE LOST as 
the result of any format operation and so any attempt to read blocks which have not been written to will result in 
unpredictable behavior.
• FCERT (Format Certification) bit determines whether the certification step will be performed during a Format Unit 
command. FCERT bit set to 0 disables certification. FCERT bit set to 1 enables the certification step.
•  BYPS  (Bypass) controls the drive's actions following a self-initiated reset.  If set, the drive will bypass both ports, and 
remain bypassed when all reset actions are complete.  In this mode, intended for development and qualification use, a 
power cycle is required to re-establish loop communications.  If the BYPS bit is zero, the drive will temporarily 
bypass both ports during the reset, but enable both when the reset actions are complete.  A unit attention condition 
will be reported to indicate that the self-initiated reset has occurred.
•  HIM (High Impedance Mode) bit determines how the drive will communicate with an 8067 compliant enclosure. When 
this bit is set to one, the drive configures its enclosure services bus drivers tobe standard open collector outputs. 
When set to zero, the drive will actively drive the bus lines high, rather than rely on an external pull-up resistor.