Marvel 88F6281 User Manual
88F6281
Hardware Specifications
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E
Copyright © 2008 Marvell
Page 28
Document Classification: Proprietary Information
December 2, 2008, Preliminary
1.2.6
Gigabit Ethernet Port Interface Pin Assignments
For additional information about the Gigabit Ethernet port pin functions refer to
.
Table 8:
Gigabit Ethernet Port0/1 Interface Pin Assignments
P i n N a m e
I / O
P i n
Ty p e
Ty p e
P o w e r
R a i l
R a i l
D e s c r i p t i o n
Port0—Dedicated GbE Pins
GE_TXCLKOUT
t/s
O
O
CMOS
VDD_GE_A
RGMII Transmit Clock
RGMII transmit reference output clock for GE_TXD[3:0] and
GE_TXCTL.
Provides 125 MHz, 25 MHz or 2.5 MHz clock.
Not used in MII/MMII mode.
RGMII transmit reference output clock for GE_TXD[3:0] and
GE_TXCTL.
Provides 125 MHz, 25 MHz or 2.5 MHz clock.
Not used in MII/MMII mode.
I
MII/MMII Transmit Clock
MII/MMII transmit reference clock from PHY.
Provides the timing reference for the transmission of the MII
transmit clock, transmit enable, and GE_TXD[3:0] signals. This
clock operates at 2.5 MHz or 25 MHz.
MII/MMII transmit reference clock from PHY.
Provides the timing reference for the transmission of the MII
transmit clock, transmit enable, and GE_TXD[3:0] signals. This
clock operates at 2.5 MHz or 25 MHz.
t/s
O
O
GMII Transmit Clock
Provides the timing reference for the transfer of the transmit
enable, transmit error and transmit data signals. This clock
operates at 125 MHz.
Provides the timing reference for the transfer of the transmit
enable, transmit error and transmit data signals. This clock
operates at 125 MHz.
GE_TXD[3:0]
t/s
O
O
CMOS
VDD_GE_A
RGMII Transmit Data
Contains the transmit data nibble outputs that run at double data
rate with bits [3:0] driven on the rising edge of GE_TXCLKOUT
and bits [7:4] driven on the falling edge.
Contains the transmit data nibble outputs that run at double data
rate with bits [3:0] driven on the rising edge of GE_TXCLKOUT
and bits [7:4] driven on the falling edge.
MII/MMII Transmit Data
Contains the transmit data nibble outputs that are synchronous
to the transmit clock input.
Contains the transmit data nibble outputs that are synchronous
to the transmit clock input.
GMII Transmit Data
Contains the transmit data nibble outputs.
Contains the transmit data nibble outputs.
GE_TXCTL t/s
O
CMOS
VDD_GE_A
RGMII Transmit Control
Transmit control synchronous to the GE_TXCLKOUT output
rising/falling edge.
GE_TXEN is driven on the rising edge of GE_TXCLKOUT.
A logical derivative of transmit enable and transmit error is driven
on the falling edge of GE_TXCLKOUT.
Transmit control synchronous to the GE_TXCLKOUT output
rising/falling edge.
GE_TXEN is driven on the rising edge of GE_TXCLKOUT.
A logical derivative of transmit enable and transmit error is driven
on the falling edge of GE_TXCLKOUT.
MII/MMII Transmit Enable
Indicates that the packet is being transmitted to the PHY. It Is
synchronous to transmit clock.
Indicates that the packet is being transmitted to the PHY. It Is
synchronous to transmit clock.
GMII Transmit Enable
Indicates that the packet is being transmitted to the PHY.
It Is synchronous to GE_TXCLKOUT.
Indicates that the packet is being transmitted to the PHY.
It Is synchronous to GE_TXCLKOUT.