Motorola MC68HC05RC8 User Manual
Interrupts
Hardware Interrupts
MC68HC05RC16 — Rev. 3.0
General Release Specification
MOTOROLA
Interrupts
41
4.6 Hardware Interrupts
All hardware interrupts except RESET are maskable by the I bit in the
CCR. If the I bit is set, all hardware interrupts (internal and external) are
disabled. Clearing the I bit enables the hardware interrupts. The three
types of hardware interrupts are explained in the following sections.
CCR. If the I bit is set, all hardware interrupts (internal and external) are
disabled. Clearing the I bit enables the hardware interrupts. The three
types of hardware interrupts are explained in the following sections.
4.7 External Interrupt (IRQ/Port B Keyscan)
The IRQ pin provides an asynchronous interrupt to the CPU. A block
diagram of the IRQ function is shown in
diagram of the IRQ function is shown in
.
NOTE:
The BIH and BIL instructions will apply to the level on the IRQ pin itself
and to the output of the logic OR function with the port B IRQ interrupts.
The states of the individual port B pins can be checked by reading the
appropriate port B pins as inputs.
and to the output of the logic OR function with the port B IRQ interrupts.
The states of the individual port B pins can be checked by reading the
appropriate port B pins as inputs.
The IRQ pin is one source of an external interrupt. All port B pins
(PB0–PB7) act as other external interrupt sources if the pullup feature is
enabled as specified by the user.
(PB0–PB7) act as other external interrupt sources if the pullup feature is
enabled as specified by the user.
Figure 4-2. IRQ Function Block Diagram
IRQ
LATCH
R
IRQ PIN
LEVEL
(MASK OPTION)
TO IRQ
PROCESSING
IN CPU
PROCESSING
IN CPU
PORT B KEYSCAN
INTERRUPT
TO BIH & BIL
INSTRUCTION
SENSING
INSTRUCTION
SENSING
RST
IRQ VECTOR FETCH
V
DD
EIMSK