The core timer for this device is a 14-stage multifunctional ripple counter.
Features include timer overflow, power-on reset (POR), real-time
interrupt (RTI), and COP watchdog timer.

As seen in

Figure 8-1

, the internal peripheral clock is divided by four,

and then drives an 8-bit ripple counter. The value of this 8-bit ripple
counter can be read by the CPU at any time by accessing the core timer
counter register (CTCR) at address $09. A timer overflow function is
implemented on the last stage of this counter, giving a possible interrupt
rate of the internal peripheral clock (E)/1024. This point is then followed
by three more stages, with the resulting clock (E/4096) driving the
real-time interrupt circuit (RTI). The RTI circuit consists of three divider
stages with a one-of-four selector. The output of the RTI circuit is further
divided by eight to drive the mask optional COP watchdog timer circuit.
The RTI rate selector bits and the RTI and CTOF enable bits and flags
are located in the timer control and status register at location $08.