Motorola MVME187 User Manual
2-10
Board Level Hardware Description
2
MEMC040 Memory Controller ASIC
The MEMC040 memory controller ASIC provides the
programmable interface for the parity-protected DRAM mezzanine
board.
programmable interface for the parity-protected DRAM mezzanine
board.
MCECC Memory Controller ASIC
The MCECC memory controller ASIC provides the programmable
interface for the ECC-protected DRAM mezzanine board.
interface for the ECC-protected DRAM mezzanine board.
Functional Description
The major functional blocks of the MVME187 covered in this
section are:
section are:
❏
Front panel switches and LED indicators
❏
Data bus structure
❏
M88000 MPU
❏
EPROM
❏
SRAM
❏
Onboard DRAM
❏
Battery backed up RAM and clock
❏
VMEbus interface
❏
I/O interfaces
❏
Local resources