Motorola MVME1X7P User Manual
Functional Blocks
http://www.motorola.com/computer/literature
2-15
2
Tick Timers
The VMEchip2 includes two general-purpose tick timers. These timers can
be used to generate interrupts at various rates or the counters can be read
at various times for interval timing. The timers have a resolution of 1
be used to generate interrupts at various rates or the counters can be read
at various times for interval timing. The timers have a resolution of 1
µ
s.
When free running, they roll over every 71.6 minutes.
Each tick timer has a 32-bit counter, a 32-bit compare register, a 4-bit
overflow register, an enable bit, an overflow clear bit, and a
clear-on-compare enable bit. The counter is readable and writable at any
time. When enabled in free-run mode, it increments every 1
overflow register, an enable bit, an overflow clear bit, and a
clear-on-compare enable bit. The counter is readable and writable at any
time. When enabled in free-run mode, it increments every 1
µ
s. When the
counter is enabled in clear-on-compare mode, it increments every 1
µ
s until
the counter value matches the value in the compare register. When a match
occurs, the counter is cleared. When a match occurs, in either mode, an
interrupt is sent to the local bus interrupter and the overflow counter is
incremented. An interrupt to the local bus is only generated if the tick timer
interrupt is enabled by the local bus interrupter. The overflow counter can
be cleared by writing a 1 to the overflow clear bit.
occurs, the counter is cleared. When a match occurs, in either mode, an
interrupt is sent to the local bus interrupter and the overflow counter is
incremented. An interrupt to the local bus is only generated if the tick timer
interrupt is enabled by the local bus interrupter. The overflow counter can
be cleared by writing a 1 to the overflow clear bit.
Tick timer 1 or 2 can be programmed to generate a pulse on the VMEbus
IRQ1 interrupt line at the tick timer period. This provides a broadcast
interrupt function which allows several VME boards to receive an interrupt
at the same time. In certain applications, this interrupt can be used to
synchronize multiple processors. This interrupt is not acknowledged on the
VMEbus. This mode is intended for specific applications and is not
defined in the VMEbus specification.
IRQ1 interrupt line at the tick timer period. This provides a broadcast
interrupt function which allows several VME boards to receive an interrupt
at the same time. In certain applications, this interrupt can be used to
synchronize multiple processors. This interrupt is not acknowledged on the
VMEbus. This mode is intended for specific applications and is not
defined in the VMEbus specification.
Watchdog Timer
The watchdog timer has a 4-bit counter, four clock select bits, an enable
bit, a local reset enable bit, a SYSRESET enable bit, a board fail enable bit,
counter reset bit, WDTO status bit, and WDTO status reset bit.
bit, a local reset enable bit, a SYSRESET enable bit, a board fail enable bit,
counter reset bit, WDTO status bit, and WDTO status reset bit.
When enabled, the counter increments at a rate determined by the clock
select bits. If the counter is not reset by software, the counter reaches its
terminal count. When this occurs, the WDTO status bit is set; and if the
local or SYSRESET function is enabled, the selected reset is generated; if
the board fail function is enabled, the board fail signal is generated.
select bits. If the counter is not reset by software, the counter reaches its
terminal count. When this occurs, the WDTO status bit is set; and if the
local or SYSRESET function is enabled, the selected reset is generated; if
the board fail function is enabled, the board fail signal is generated.