Motorola MVME1X7P User Manual
LCSR Programming Model
http://www.motorola.com/computer/literature
2-53
2
.
DMAC Registers
This section provides addresses and bit level descriptions of the DMAC
counters, control registers, and status registers. Other control functions are
also included in this section.
counters, control registers, and status registers. Other control functions are
also included in this section.
EPROM Decoder, SRAM and DMA Control Register
This register controls the snoop control bits used by the DMAC when it is
accessing table entries.
accessing table entries.
SRAMS
These VMEchip2 bits are not used on the MVME1x7P.
Table 2-3. DMAC Command Packet Format
Entry
Function
0 (bits 0-15)
--
Control Word
1 (bits 0-31)
Local Bus Address
2 (bits 0-31)
VMEbus Address
3 (bits 0-31)
Byte Count
4 (bits 0-31)
Address of Next Command Packet
ADR/SIZ
$FFF40030 (8 bits [6 used] of 32)
BIT
23
22
21
20
19
18
17
16
NAME
WAIT RMW
ROM0
TBLSC
SRAMS
OPER
R/W
R/W
R/W
R/W
RESET
0 PSL
1 PSL
0 PS
0 PS