Motorola MVME1X7P User Manual
2-86
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VMEchip2
2
CVI1E
Clear VMEbus IRQ1 edge-sensitive interrupt.
CPE
Not used on MVME1x7P.
CMWP
Clear VMEbus master write post error interrupt.
CSYSF
Clear VMEbus SYSFAIL interrupt.
CAB
Not used on MVME1x7P.
CACF
Clear VMEbus ACFAIL interrupt.
Interrupt Clear Register (bits 16-23)
This register is used to clear the edge-sensitive interrupts. An interrupt is
cleared by writing a 1 to its clear bit. The clear bits are defined below.
cleared by writing a 1 to its clear bit. The clear bits are defined below.
CLM0
Clear GCSR LM0 interrupt.
CLM1
Clear GCSR LM1 interrupt.
CSIG0
Clear GCSR SIG0 interrupt.
CSIG1
Clear GCSR SIG1 interrupt.
CSIG2
Clear GCSR SIG2 interrupt.
CSIG3
Clear GCSR SIG3 interrupt.
CDMA
Clear DMA controller interrupt.
CVIA
Clear VMEbus interrupter acknowledge interrupt.
ADR/SIZ
$FFF40074 (8 bits of 32)
BIT
23
22
21
20
19
18
17
16
NAME
CVIA
CDMA
CSIG3
CSIG2
CSIG1
CSIG0
CLM1
CLM0
OPER
C
C
C
C
C
C
C
C
RESET
X
X
X
X
X
X
X
X