Motorola MVME1X7P User Manual
LCSR Programming Model
http://www.motorola.com/computer/literature
2-91
2
Interrupt Level Register 2 (bits 0-7)
This register is used to define the level of the GCSR LM0 interrupt and the
GCSR LM1 interrupt.
GCSR LM1 interrupt.
LM0 LEVEL These bits define the level of the GCSR LM0 interrupt.
LM1 LEVEL These bits define the level of the GCSR LM1 interrupt.
Interrupt Level Register 3 (bits 24-31)
This register is used to define the level of the software 6 interrupt and the
software 7 interrupt.
software 7 interrupt.
SW6 LEVEL These bits define the level of the software 6 interrupt.
SW7 LEVEL These bits define the level of the software 7 interrupt.
ADR/SIZ
$FFF4007C (8 bits [6 used] of 32)
BIT
7
6
5
4
3
2
1
0
NAME
LM1 LEVEL
LM0 LEVEL
OPER
R/W
R/W
RESET
0 PSL
0 PSL
ADR/SIZ
$FFF40080 (8 bits [6 used] of 32)
BIT
31
30
29
28
27
26
25
24
NAME
SW7 LEVEL
SW6 LEVEL
OPER
R/W
R/W
RESET
0 PSL
0 PSL