Motorola MVME1X7P User Manual
xxii
Overview of Contents
, describes the board-level hardware
features of MVME1X7P single-board computers. It includes memory
maps and a discussion of some general software considerations such as
cache coherency, interrupts, and bus errors.
maps and a discussion of some general software considerations such as
cache coherency, interrupts, and bus errors.
, describes the VMEchip2 ASIC, the local
bus/VMEbus interface chip on MVME1X7P boards.
, describes the PCCchip2 ASIC. The PCChip2 is a
peripheral channel controller designed to interface an MC680x0-
compatible local bus to various on-board peripheral devices such as SCSI
and LAN controllers.
compatible local bus to various on-board peripheral devices such as SCSI
and LAN controllers.
, describes the ECC DRAM controller ASIC
(MCECC). On the MVME1X7P boards, it supplies the interface to a 144-
bit wide DRAM memory system.
bit wide DRAM memory system.
, lists the modifications that
accompanied the introduction of the Petra ASIC on the MVME167P and
MVME177P.
MVME177P.
, contains drawings of
the printer and serial port interface connections available with the
MVME167P/MVME177P and MVME712 series transition board.
MVME167P/MVME177P and MVME712 series transition board.
, lists all documentation related to the
MVME167P and MVME177P.
Comments and Suggestions
Motorola welcomes and appreciates your comments on its documentation.
We want to know what you think about our manuals and how we can make
them better. Mail comments to:
We want to know what you think about our manuals and how we can make
them better. Mail comments to:
Motorola Computer Group
Reader Comments DW164
2900 S. Diablo Way
Tempe, Arizona 85282
Reader Comments DW164
2900 S. Diablo Way
Tempe, Arizona 85282