Motorola MVME1X7P User Manual
Functional Description
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Functional Description
The following sections provide an overview of the functions provided by
the Petra MCECC sector. For a detailed programming model for the
Petra/MCECC control and status registers, refer to the Programming
Model section.
the Petra MCECC sector. For a detailed programming model for the
Petra/MCECC control and status registers, refer to the Programming
Model section.
General Description
The Petra MCECC sector is a single-chip solution for memory control
functions. The memory architecture is a single bank of SDRAM, 32 bits
wide plus seven check bits. The MCECC sector provides all the functions
required to implement a memory system. These include programmable
map decoding, memory control, refresh, and a memory scrubber. The
scrubber, when enabled, periodically scans memory for errors. If the
scrubber finds a single-bit error in the memory array, it corrects the error.
This prevents soft single-bit errors from becoming double-bit errors.
functions. The memory architecture is a single bank of SDRAM, 32 bits
wide plus seven check bits. The MCECC sector provides all the functions
required to implement a memory system. These include programmable
map decoding, memory control, refresh, and a memory scrubber. The
scrubber, when enabled, periodically scans memory for errors. If the
scrubber finds a single-bit error in the memory array, it corrects the error.
This prevents soft single-bit errors from becoming double-bit errors.
Performance
The Petra MCECC sector maintains tags for each internal bank of
SDRAM. Each bank may be in an active or idle state. SDRAM access time
is a function of the state of the bank of memory being addressed. If the
bank addressed is active, performance is additionally a function of the page
of memory being referenced. If the page referenced is open, access time is
the shortest possible. Maximum access time will occur when the page
referenced is not open, since the open page must be first closed and the
desired page then opened.
SDRAM. Each bank may be in an active or idle state. SDRAM access time
is a function of the state of the bank of memory being addressed. If the
bank addressed is active, performance is additionally a function of the page
of memory being referenced. If the page referenced is open, access time is
the shortest possible. Maximum access time will occur when the page
referenced is not open, since the open page must be first closed and the
desired page then opened.
Page sizes are determined by the configuration of the SDRAM device.
Sizes range from 256 to 1024 memory locations per page.
Sizes range from 256 to 1024 memory locations per page.
The Petra MCECC sector design is targeted for SDRAM devices of the
PC100 type. Memory access time are not influenced by the settings of
mode bits or SDRAM speed selections.
PC100 type. Memory access time are not influenced by the settings of
mode bits or SDRAM speed selections.
The basic performance specifications for the MCECC sector are listed in