Motorola MVME1X7P User Manual

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Programming Issues
Introduction
The MVME167P and MVME177P single-board computers are complex 
boards that interface both to the VMEbus and the SCSI bus. From a 
programming standpoint, their multiple-bus interfaces raise issues of 
cache coherency and support of indivisible cycles. There are also various 
potential sources of bus error. 
This chapter discusses those topics in addition to interrupt handling, the 
use of bus timers, and the programming interface to each device on the 
board. Programmable registers that reside in ASICs (Application-Specific 
Integrated Circuits) on the MVME1X7P boards are covered in the chapters 
devoted to those devices.
Note
The MVME1X7P’s new ’‘Petra’’ ASIC performs the functions 
previously implemented in the MCECC chip. For ease of use in 
conjunction with programming models and documentation 
developed for earlier boards, however, the structure of this 
manual preserves the functional distinctions that formerly 
characterized the MCECC ASIC.
The Petra ASIC and Second-Generation MVME1X7 Boards
Due to rapid changes in technology, the production of certain ASICs used 
on various Motorola first- and second-generation VME embedded 
controllers and single-board computers has ended. The Petra chip was 
developed to replace these discontinued ASICs. In the case of 
MVME167/177 series boards, the discontinued ASIC is the MCECC chip. 
The Petra chip now supplies the functions formerly implemented in the 
MCECC chip.