Motorola MVME5100 Series User Manual

face signals to the MVME712M transition module. The 3-row
P2 adapter can be used for 8-bit SCSI.

To gain access to the additional user definable I/O pins pro-
vided via the 5-row VME64 extension connector, a special P2
adapter board is available. This adapter panel replaces the
traditional 3-row P2 adapter and extends its capability by pro-
viding access to the PMC I/O pins.

S o f t w a r e S u p p o r t

Firmware Monitor
Firmware must fulfill the traditional functions of test and initial-
ization and provide operating system boot support. The
MVME5100 firmware monitor exceeds these requirements
with a proven monitor from the embedded VME leader. It
expands features like power-up tests with extensive diagnos-
tics, as well as a powerful evaluation and debug tool for sim-
ple checkout or when high-level development debuggers
require additional support. All this is included with the
MVME5100 firmware; plus it supports booting both operating
systems and kernels.

Operating Systems and Kernels
MVME5100 supports booting a variety of operating systems
including a complete range of real-time operating systems
and kernels which may be purchased from the following com-
panies:

S p e c i f i c a t i o n s

M V M E 5 1 0 0 P r o c e s s o r M o d u l e

Processor

Main Memory

Flash Memory

NVRAM

Counters/Timers

VMEbus ANSI/VITA 1-1994 VME64 (IEEE STD 1014)

Ethernet Interface

Asynchronous Serial Ports

Dual IEEE P1386.1 PCI Mezzanine Card Slots

Wind River Systems, Inc.:

VxWorks

Multiple Partners:

Linux

Microprocessor:

MPC7400

MPC750

Clock Frequency:

400 MHz

450 MHz

On-chip Cache (I/D):

32K/32K

Secondary Cache:

1MB or 2MB

1MB

Type:

PC100 ECC SDRAM with 100 MHz bus

Capacity:

64MB, 128MB, or 512MB on board,
expandable to 1GB with RAM500 mem-
ory mezzanines

Single Cycle Accesses:

10 Read/5 Write

Read Burst Mode:

7-1-1-1 idle; 2-1-1-1 aligned page hit

Write Burst Mode:

4-1-1-1 idle; 2-1-1-1 aligned page hit

Architecture:

64-bit, single interleave

S o f t w a r e S u p p o r t

S p e c i f i c a t i o n s

MVME5100 Processor Module

Type:

EEPROM, on-board programmable

Capacity:

1MB via two 32-pin PLCC/CLCC sockets;
16MB surface mount

Read Access (16MB

port):

70 clocks (32-byte burst)

Read Access (1MB

port):

262 clocks (32-byte burst)

Capacity:

32KB (4KB available for users)

Cell Storage Life:

50 years at 55° C

Cell Capacity Life:

5 years at 100% duty cycle, 25° C

Removable Battery:

Yes

TOD Clock Device:

M48T37V

Real-Time Timers/

Counters:

Four, 32-bit programmable

Watchdog Timer:

Time-out generates reset

Controller:

Tundra Universe

DTB Master:

A16–A32; D08–D64, BLT

DTB Slave:

A24–A32; D08–D64, BLT, UAT

Arbiter:

RR/PRI

Interrupt Handler/

Generator:

IRQ 1–7/Any one of seven IRQs

System Controller:

Yes, jumperable or auto detect

Location Monitor:

Two, LMA32

Controller:

Two Intel 82559ER

Interface Speed:

10/100Mb/s

PCI Local bus DMA:

Yes, with PCI burst

Connector:

One routed to front panel RJ-45, one
routed to front panel RJ-45 or optionally
routed to P2, RJ-45 on MVME761

Controller:

16C550C UART

Number of Ports:

Two, 16550 compatible

Configuration:

EIA-574 DTE

Async Baud Rate, bps

max.:

38.4K EIA-232, 115Kbps raw

Connector:

One routed to front panel RJ-45, one on
planar for development use

Address/Data:

A32/D32/D64, PMC PN1, PN2, PN3,
PN4 connectors

PCI Bus Clock:

33 MHz

Signaling:

Power:

+3.3V, +5V,

12V; 7.5 watts maximum

per PMC slot

Module Types:

Two single-wide or one double-wide, front
panel or P2 I/O